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stage accuracy problem in pipeline ADC

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zyyang

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Dear all,
i still have another problem in calculating stage accuracy for pipeline ADC.
i am giving out the spec of any module according to the calculating. so for any stage, including THA, residue1,residue2, i will calculate the actual output for any stage, and get all of the errors for any stage, if the summing of the error is smaller than 0.5LSB of the residue stages, then the accuracy is enough, for example, for residue1 output error, it the summing is smaller than 0.5*1/2^(N-1), then residue1 accuracy is enough.

However, for a 10bit ADC, and the gain is 2 for any residue stage, which means 1.5bit/stage, the output of THA is equal to Vin+error, the error is due to the non-ideal of THA, and error<0.5LSB=0.5*(1/2^10)=1/2^11; but the output(Vin+error) of THA will enter residue1 as a input signal for residue1, therefore, the error from THA will be multi-by 2, so even if the residue1 has no any error, only the THA error will be (1/2^11)*2=1/2^10=0.5*(1/2^9), it means the required 0.5LSB error margin for residue1 has been eated by the error from THA, so the error from the residue1 will make residue1 accuracy can not satisfy 9bit requirement.

how do you think of this problem, thanks!

Zhenyu
 

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