stability analysis and error amplifier design of PWM switching converter

[viperpaki007]

Hi,

I am designing PWM based integrated DC-DC converter operating at 300MHz clock frequency. I need to do the stability analysis of whole circuit inorder to check whether the whole feeback system is stable or not. What kind of simulations i should do for that in cadence spectre RF?. What kind of error amplifier will be suitable for this kind of system.

regards

 

[tgootee]

Will you be able to plot open-loop gain and phase equivalents?

Edit: Since you don't yet have the feedback error amplifier designed, you should simply design the feedback in such a way that it will be guaranteed to have your choice of stability margins. The simulation would then only be used to check that your results are correct.

 

[viperpaki007]

i dont have any idea which kind of design equations i should use to get the overall stability margins....Moreover, what kind of simulations i should use in cadence to check stability. Can you please give me any link to study

 

[tgootee]

http://www.ee.bgu.ac.il/~pel/presentation/PET06/PET06.pdf

http://www.onsemi.com/pub_link/Collateral/TND352-D.PDF

http://www.intersil.com/content/dam/Intersil/documents/tb41/tb417.pdf

http://www.ti.com/lit/an/slva301/slva301.pdf

http://www.irf.com/technical-info/appnotes/an-1162.pdf

**broken link removed**

**broken link removed**

 

[dick_freebird]

I am curious just how you intend to obtain square wave
switching at 300MHz, at any kind of power. Because I'm
finding it "interesting" at 50MHz.

 

[tgootee]

What kind of hardware implementation are you trying to use? Without using a pro-manufactured multilayer PCB, with separate planes for each power rail and ground, and controlled-impedance lines, it might be tough. And even then, it would probably be tough. Low inductance is one of the magic words, one translation of which is short distances. Decoupling caps' placements (i.e. connection lengths), and type and sizewould be extremely important

 

[viperpaki007]

Hi,

Thanks for the help. I am designing the converter on 65nm CMOS process. The design requirements require high bandwidth operation from DC-DC converter. Therefore, using high switching frequency is necessary. Currently i am using an ideal clock source to drive the converter and checking what will be a more practical switching frequency for converter.