May 3, 2022 #1 P promach Advanced Member level 4 Joined Feb 22, 2016 Messages 1,199 Helped 2 Reputation 4 Reaction score 5 Trophy points 1,318 Activity points 11,636 I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and write_clk are having the same clock frequency. Could anyone advise ?
I have implemented an asynchronous FIFO However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees. Both read_clk and write_clk are having the same clock frequency. Could anyone advise ?
May 4, 2022 #2 S std_match Advanced Member level 4 Joined Jul 9, 2010 Messages 1,304 Helped 463 Reputation 926 Reaction score 448 Trophy points 1,363 Location Sweden Activity points 10,176 1. Don't use the "simplify" full/empty options 2. Set all clock domain crossing signals as "false paths". Upvote 0 Downvote
1. Don't use the "simplify" full/empty options 2. Set all clock domain crossing signals as "false paths".