Hi ivlsi,
STD cells are blackboxes for synthesizer and for P&R tools. They're usually described as separate timing-power model with NLDM tables (or with extensions - CCS, ECSM) and geometric abstract information for P&R tools. Each STA tool uses propagation delays from timing library regardless of project stage - pre- or layout stage. The difference in timing calculation at the synthesis stage and layout stage is that in synthesis stage there are no information about interconnections between cells and timing calculation is based on wireload models or something like that. But at the layout stage it is possible to extract parasitic values and obtain more accurate data.
Hope it was helpful.
Best regards,
Kuxx.