Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

STA issue about clock gating

Status
Not open for further replies.

andy.huang

Newbie level 3
Joined
Jul 22, 2016
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
28
Hi,

i used design compiler to synthesis a clock gating circuit automatically.

the clock path is : clk(create clock) -> latch -> DFF/CP

and there comes a problem, the DFFs connected by the gated clock are all un-constraint with the reason "no-clock",

does it the clock constraint cannot pass latch ? how can i solved this issue , thanks.
 

slutarius

Full Member level 5
Joined
Oct 30, 2015
Messages
248
Helped
37
Reputation
74
Reaction score
36
Trophy points
28
Activity points
1,540
You have to check the posibility of your project to use latch in the design.
Secondly, check the enable signal of the latch whether it is fixed to LOW or not.
 

andy.huang

Newbie level 3
Joined
Jul 22, 2016
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
28
thanks for reply.
i checked, latch is allowed for clock gated, and its enable pin comes from combination logic
 

slutarius

Full Member level 5
Joined
Oct 30, 2015
Messages
248
Helped
37
Reputation
74
Reaction score
36
Trophy points
28
Activity points
1,540
Check the setting in tool behavior about clock signal propagation. When it is OFF, clock can not go through sequential device like latch cells.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top