maulin sheth
Advanced Member level 2
- Joined
- Oct 24, 2010
- Messages
- 502
- Helped
- 90
- Reputation
- 179
- Reaction score
- 90
- Trophy points
- 1,318
- Location
- Bangalore, India
- Activity points
- 4,161
Hello All,
Suppose ff1 is -> +ve edge clock
ff2 is -> -ve edge clock
ff1/q connected to ff2/input. and clock are same. Just first one is +ve edge triggered and 2nd one is -ve edge triggered flop.
Now,
My doubt is -> why we can not load ff1 and ff2 in the single clock cycle?
We are using lock up latch for this purpose only (we can not load two data in single pulse).
Thanks & Regards,
Maulin
Suppose ff1 is -> +ve edge clock
ff2 is -> -ve edge clock
ff1/q connected to ff2/input. and clock are same. Just first one is +ve edge triggered and 2nd one is -ve edge triggered flop.
Now,
My doubt is -> why we can not load ff1 and ff2 in the single clock cycle?
We are using lock up latch for this purpose only (we can not load two data in single pulse).
Thanks & Regards,
Maulin