STA corners of digital chip

[shobhit]

while performing post layout STA of digital chips we create many corners say QCMAX, QCMIN, RMAX, RMIN, .....etc etc, where these corners vary in VDD, Temp, Process and obviously the extractions (Resistance or capacitance or coupling capacitance)
although we know that setup violations would be worse in 1 corner (QCMAX) and hold would be worse in (QCMIN) then why do we need so many corners?


Plz help frnds......I cant figure out the reason...

 

[analogLow]

I am not familiar with Qcmax, Qcmin, etc. but I do understand that after you have run your parasitic extraction (and generated a new .cir), that it would be best to test all global and local variations on this new .cir file.

 

[bschaitanya]

gud question.. At lower nodes its very difficult to predict circuit behavior on silicon. In general for more robustness of the chip we adding up different corners to check whether timing met or not. At lower nodes temperature inversion plays the key role.

 

[analogLow]

The models (e.g. BSIM, EKV) are ok down to lower voltages than the threshold. I have the models for a 65nm process accurate down to 0.3V. Of course, the newer the process, the less accurate. The models get better as the vendor does more runs and records the variation distributions. The best you can do is run all combinations of global and local variations (e.g. temp, global process corners, and local variation). However, if you want what I call "research robust", then I think running global process corners (FF,FS,SF,TT,SS) and Monte-Carlo at each of these corners should be enough. If you are building a real product, then of course you need to also include temperature, which makes the simulations much more time consuming.

Good luck,
analogLow