Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

STA commands for debugging all violation

Status
Not open for further replies.

mepriyasingh

Member level 2
Joined
Sep 20, 2015
Messages
42
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
255
Please give brief commands knowledge about how to debug setup,hold out_setp,out_hold, clock gating , recovery and removal using different commands,
Please give commands which are generally use during debugging and how each violation can be remove by commands.
Thanks in Advance
 

In Primetime, the reporting command,
report_constraints -max_transition ...
report_timing ...

To fix the timing / drc violations,
fix_eco_drc, fix_eco_timing

:::::::::::::::::

If you want specific reports, you may have to play with the options. To report timing only related to clock gating, try reading the options in help or solvnet website.
 

Please explain me more about "report_bottleneck" in what situation we can use it as a powerful command

Thanks
 

need few explanation in which situtation we use the command and what is the importance

Thanks
 

Evey STA tool has a command reference manual. Please refer to that for the usage and explanations of commands.
 

report_bottleneck can be used when you've more viol, this will report the common points.

You will address the violations in bulk if you touch the common point.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top