STA by primetime and violation

[sun_ray]

What are the different technique to close the timing if timing vilations are found during STA by primetime? Is there any tool related technique to resolve timing violation while doing STA by primetime?

 

[rca]

Primetime povides command to fix the drv violations for example. The needed std cell modification could be written in ascii file for ICC.
if you used Encounter, a quick and easy script could be used to read the ICC file to transform in Encounter command the required std cell up/down size or to add.

 

[sun_ray]

What do you mean by drv? Can you please explain more about "The needed std cell modification could be written in ascii file for ICC"?

But you replied that STA cannot solve violation , it only reports violation in the thread titled static timing analaysis.

Thanks for the reply.

 

[rca]

DRV covers transition/load/fanout violations.

STA is only to reports timing and others violations (clock pulse, trans/load, connection class ....) with "report_constraint" command.

Primetime do the STA and could fix the DRV by inserterd/sizing std cells, used the following command "fix_eco_drc", and "write_changes".

 

[sun_ray]

DRV covers transition/load/fanout violations.

This is not DRV, but DRC.

Regards,

 

[rca]

Sorry, I mix with Encounter:
DRC is more related to layout rule checks.
DRV for the trans/cap/fanout violations.

 

[soloktanjung]

Hi,

I know about fix_eco_timing but have not tried it yet. Maybe you can consider it. Link:

https://www.edaboard.com/threads/221222/

https://www.edaboard.com/threads/248811/