Two configurations are available upon order.
SST26VF064B default at power-up has the WP# and
HOLD# pins enabled, and the SIO2 and SIO3 pins disabled,
to initiate SPI-protocol operations.
SST26VF064B / SST26VF064BA
2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory
SST26VF064B / SST26VF064BA
DS20005119G-page 2 2015 Microchip Technology Inc.
SST26VF064BA default at power-up has the WP# and
HOLD# pins disabled, and the SIO2 and SIO3 pins
enabled, to initiate Quad I/O operations. See “I/O Configuration
(IOC)” on page 12 for more information about
configuring WP#/HOLD# and SIO3/SIO4 pins