[SOLVED] SSI interface ? hardware vs software

[Electro nS]

hey guys

just wondering if anyone is familiar with the SSI interface (serial syncronous interface)

it is unidirectional communication technique on rs422 drivers for long distance

the problem i am having is inconsistent readings on a very short 10 feet cable !!

the inconsistacy is usually one bit and is never in the same place so data is received but distorted and off course this protocol doesnot require checksum or correction bits .

note : i am using a PIC microcontroller at 40mips , 2 simple GPIO for the communication at 100khz to 1Mhz clock, with serial com at 9600 port to view the data on PC . and very simple software which i am sure is 100% working

so any advise on solving the problem , could using dedicated SPI module with manual manipulation of the configuration bits be done to improve the results ?? could i use schmitt triggers and filter ?? or a specific ICs latches for hardware decoding

 

[HTA]

Hi Electro ns,

since SSI is a synchronous type of serial transfer and you generate the master clock it can be generated in software if you meet the timing of the device connected. The general SSI description can be found here: https://en.wikipedia.org/wiki/Synchronous_Serial_Interface . There are some differences from MFG to MFG and you need to have the timing requirement of the device you use. There is a setup and hold time, maximum clock speed and time out at the end you need to considered. Also no clock spikes are tolerable. At the beginning of the cycle you could check in software if the data line is high.

Enjoy your design work!

 

[Electro nS]

Hi Electro ns,

since SSI is a synchronous type of serial transfer and you generate the master clock it can be generated in software if you meet the timing of the device connected. The general SSI description can be found here: https://en.wikipedia.org/wiki/Synchronous_Serial_Interface . There are some differences from MFG to MFG and you need to have the timing requirement of the device you use. There is a setup and hold time, maximum clock speed and time out at the end you need to considered. Also no clock spikes are tolerable. At the beginning of the cycle you could check in software if the data line is high.

Enjoy your design work!

THANKS for your reply
i followed all these things , except for clock SPIKES , i have connected an oscilloscope and i can clearly see the spikes generated , any proposed solution ?

 

[HTA]

That is part of your emulation software sequence. Is it written in assembler or HLL?

Enjoy your design work!

 

[Electro nS]

That is part of your emulation software sequence. Is it written in assembler or HLL?

Enjoy your design work!

c code mplab , syntex looks like this very simple:

clk low  // inialize a request 
delay 1us 
clk high  
x=messageSize
while (x>=0)
{
delay 1us 
clk low
if Data==1 array[x] =1
else array[x]=0
delay 1us
clk high
x--;
}

please comment

 

[HTA]

The SSI cycle is fixed with a clock edge from high to low and the number of clock cycles. Any clock edge in between will cause a false read. To test that the compiler generate a clean clock signal I would do a loop with the required number of bits(defined by the device you readout) and restart it again after the defined end delay(clock high time usually 13us) to see on the oscilloscope if the clock is clean.
It is of course essential that you know the specification of the device connected.

Enjoy your design work!

 

[Electro nS]

SOLUTION SOFTWARE AND HARDWARE it is present in this application note if anyone is interseted in this subject

google this : AbsoluteEncoders_Context_Technology_SSI_AppNote