SRAM read/write access time and operating frequency

[onion2014]

Hi all,

Can anyone explain the relationship between the operating frequency and the read/write access time in sram.

Best,

- - - Updated - - -

find some answer from a manual and share the answer with guys here. but still have some question about this. Why access time can be larger/equal to the cycle time. is it because in some case the read access takes more than one clock cycle to finish?

The quoted access
time is the minimum amount of time required to read
a bit of data from the memory, measured with
respect to the initial rising clock edge in the SRAM
read operation. This access time specification is
measured under specific load, temperature, and
power supply conditions, in which all critical timings
meet the requirements set out in the product specification.

The cycle time is the amount of time required to perform
a single read or write operation and reset the
internal circuitry so that another operation can begin.
This time is usually designated by one complete
clock cycle. (See Figure 4.) In some cases, the
access time and cycle time are equal; in others,
access times may be greater or smaller than the
cycle time

 

[barry]

I think this confusion might be due to the fact that the delay from address to data valid is generally longer than the delay from chip select to data valid.