SRAM interface with fpga altera de1

[Ahme Fahmy]

hi
i want to read and write to sram from fpga with variable address , but its stuck always :sad: here is the code , if there is any mistake plz tell me


library ieee;
use ieee. std_logic_1164.all ;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sram_ctrl is
port (
clk, reset: in std_logic;
-- t o / f r o m main s y s t e m
mem: in std_logic;
--rw: in std_logic;
--addr : in std_logic_vector (17 downto 0) ;
--
ready : out std_logic ;
data_s2f_r , data_s2f_ur ut std_logic_vector (15 downto 0 ) ;
-- t o / f r o m c h i p
read_checkut std_logic;
write_checkut std_logic;
ad: out std_logic_vector (17 downto 0) ;
we_n, oe_n: out std_logic;
-- SRAM c h i p a
dio_a: inout std_logic_vector (15 downto 0 ) ;
force_reading: in std_logic;
rxd : in std_logic;
txd : out std_logic;
--cts : buffer std_logic;
--rts : in std_logic;
parallel_data : out std_logic_vector(9 downto 0);
ce_a_n, ub_a_n, lb_a_n: out std_logic

);
end sram_ctrl;
architecture arch of sram_ctrl is
type state_type is (idle, rdl, rd2, wrl, wr2);
signal saddr_wr : std_logic_vector (17 downto 0) :="000000000000000000";
signal saddr_rd : std_logic_vector (17 downto 0) :="000000000000000000";
signal parallel_data_signal : std_logic_vector ( 9 downto 0);
signal state_reg, state_next : state_type;
signal data_f2s_reg, data_f2s_next :std_logic_vector ( 15 downto 0 ) ;
signal data_s2f_reg , data_s2f_next :std_logic_vector (15 downto 0 ) ;
signal addr_reg,addr_next : std_logic_vector (17 downto 0 ) ;
signal we_buf , oe_buf , tri_buf : std_logic ;
signal we_reg , oe_reg , tri_reg: std_logic ;
signal data_f2s : std_logic_vector (15 downto 0) ;
--signal mem:std_logic;
signal rw:std_logic;
begin
process (clk,reset )
variable clk_count : integer :=0;
variable bit_count : integer :=0;
variable start : integer :=0;
variable clear : integer :=0;
variable start_flag : integer :=0;
begin
if (reset ='1') then
state_reg<=idle ;
addr_reg<=(others=>'0' ) ;
data_f2s_reg <=(others => '0' ) ;
data_s2f_reg<=(others=>'0' ) ;

tri_reg <= '1';
we_reg <= '1';
oe_reg <= '1';
elsif(clk'event and clk='1') then
if (rxd= '0') then
--start_flag is used to start counting clock pulse
start_flag:=1;
end if;
if (start_flag = 1) then
--since start_flag is set, clk_count continues counting
--it will continue until start_flag is set to 0
clk_count:= clk_count+1;
end if;
if(clk_count = 2604) then --2604 for 9600 baud[change the count for different baud(1)]
--means time to sample 9600 serial data
--at 2604 times 50MHz clock cycle from the start of the start bit
--the time is correct to sample at middle point of the received pulse
if(bit_count < 10) then
--the received data in 10 bit with start and stop bit
--so only take first 10 samples from once the start_flag is set
parallel_data_signal(bit_count) <= rxd;
--after sampling bit_count is incremented
bit_count:=bit_count+1;
elsif(bit_count = 10) then
--coupling data to output onall the 10 bits are captured
rw <= '0';

if force_reading='0' then
data_f2s(7 downto 0)<=parallel_data_signal(8 downto 1);
if saddr_wr="000000000000000011" then
saddr_wr<="000000000000000000";
end if;
saddr_wr<=saddr_wr+'1';

end if;
--once the 10 bits are captured, the start_flag is reset
start_flag:=0;
--bit_count is reset to 0
bit_count:=0;
--reseting clk_count
clk_count:=0;
end if;

elsif(clk_count = 5208) then --5208 for 9600 baud[change the count for different baud(2)]
--5208 clock pulse at 50MHz is the time for single serial pulse
--the clk_count is reset to start for the next serial pulse
clk_count:=0;
end if;
if force_reading='1' then
rw<='1';
end if;

state_reg <=state_next ;
addr_reg <=addr_next;
data_f2s_reg<=data_f2s_next ;
data_s2f_reg<=data_s2f_next;
tri_reg<=tri_buf;
we_reg <= we_buf;
oe_reg<=oe_buf;

end if ;
end process;
process ( state_reg,mem,rw,dio_a,saddr_rd,data_f2s
,data_f2s_reg,data_s2f_reg,addr_reg)

-- n e x t - s t a t e l o g i c

begin
--addr_next<=addr_reg ;
data_f2s_next <=data_f2s_reg;
data_s2f_next<=data_s2f_reg ;
ready<= '0' ;
case state_reg is
when idle=>
if mem='0' then
state_next<=idle;
write_check<='0';
read_check<='0';
else
if rw='0' then -- w r i t e
state_next<= wrl;
data_f2s_next<=data_f2s;
addr_next<=saddr_wr;
--addr_next<=saddr_wr;
else
state_next<=rdl;
addr_next<=saddr_rd;
-- r e a d
end if ;
end if ;
ready<= '1' ;
when wrl=>
state_next<= wr2;
when wr2 =>
write_check<='1';
read_check<='0';
state_next <= idle;
--saddr_wr<=saddr_wr + '1';
when rdl =>
state_next <= rd2;
when rd2=>
data_s2f_next <= dio_a;
read_check<='1';
write_check<='0';
state_next <= idle;
--saddr_rd<="000000000000100100";
if saddr_rd="000000000000000011" then
saddr_rd<= "000000000000000000";

end if;
saddr_rd<=saddr_rd+'1';
end case ;
end process ;
-- ‘I l o o k - a h e a d I‘ o u t p u t l o g i c
process(state_next)
begin
tri_buf <= '1'; -- d e f a u 1 t
we_buf <= '1';
oe_buf <= '1';
case state_next is
when idle =>
when wrl =>
tri_buf <= '0' ;
we_buf <= '0';
when wr2 =>
tri_buf <= '0' ;
when rdl =>
oe_buf <= '0' ;
when rd2=>
oe_buf <= '0' ;
end case;
end process ;
--t o main s y s t e m
data_s2f_r<= data_s2f_reg;
data_s2f_ur<=dio_a ;
--t o SRAM
we_n <= we_reg;
oe_n <= oe_reg;
ad<= addr_reg;

--i/o f o r SRAM c h i p a
ce_a_n <= '0' ;
ub_a_n <= '1' ;
lb_a_n <='0' ;
dio_a<= data_f2s_reg when tri_reg='0' else(others=>'Z') ;
end arch;

 

[willis...]

If you send me your project files I would be more than happy to take a look at it.

-Willis