SRAM-based FPGA design question

[lahrach]

Hi friends,

what is the definition of the "skew" in timing constraints and what is its importance?
regards,

 

[CCDesigner]

Skew is the time, typically measured between two signals, or groups of signals. Skew plays a big roll when it comes to designing an interface. In regards to FPGA's, the majority of designs are synchronous. So for example, lets say you have an FPGA FLASH interface and you are generating the control signals. Skew can be a measurement between the clock edge and the FLASH enable, or between the FLASH enable and the Write enable.

An easier explanation might be if you have a signal inside the FPGA that is driven by internal logic and it goes to an external pin it will have a delay before the signal gets to the pin. Take that same signal and now split it and route it out 2 different pins. Each signal will have a different delay between the logic and the pin. If you measure the time delay difference between the two pins you would get your skew.

Skew is important when you have a time dependency between the signals. Maybe Signal A has to be at an external chip at time 20 ns (max) before Signal B and they are triggered on the same clock edge. If you find out you have a skew of 50 ns because of how the FPGA routed it, then you just failed spec..

 

[lahrach]

Thank you for this great explanation, so my second question is can we medeled a skew (delay fault) with recent FPGA and ISE tool

regards!

 

[CCDesigner]

Medeled?

Did you mean modeled?

If you are simulation in the tool, yes you can model it. You can even add delays to individual signals in the FPGA code.

 

[lahrach]

yes I mean modeled, so you have told that I can add delays to signal have you an example or docs

thank you for your help in advance!