Not sure why you're saying you need exactly 10dB higher gain.
As far as the noise floor is concerned, it remains the same whether you are doing regular clocking or SSC. And the signal power would be spread over a wider bandwidth with SSC. Hence the SNR at the ADC input is expected to be poorer. This is true only if you assume that SSC is increasing the signal bandwidth compared to single frequency clock, which looks true based on your description. Hence a higher gain with the same NF is definitely desirable. You should be able to calculate the SNR and hence the required extra gain based on the SSC spread. I am not sure how you got the 10dB number.
Bottom line is like you said, at the ADC input, as long as the signal is above the noise floor, you will be able to detect it. In other words, as long as the total signal power is higher than the total noise power in the overall bandwidth of interest (i.e ADC RBW) by a certain number (required SNR), you should be able to demodulate the signal. It should not depend on the nature of clocking. However as SSC increase the bandwidth and hence the required ADC BW, if you make sure the SNR is met at the ADC input, that should be enough. Extra gain should be calculated based on the spread.