theguardian2001
Junior Member level 3
Hi everyone,
I am currently designing a fully-differential 12 bit SAR ADC using charge-scaling DAC. To reduce the total capacitance needed I have tried to investigate the behavior of such a split CDAC in MATLAB Simulink before going back to Spice and build it with the components from tech. library. When simulating split DAC I have noticed a behavior based on which one could have concluded that split CDAC concept can not be applied for my design.
Above you can see the setup: it uses L4M8-C structure emulating one side of the DAC with unit cap being 520fF based on matching and accuracy requirements, it samples input sinusoidal voltage with f=12MHz, Vcm=0.9V and V_ac=0.9V. When sampling switch turns off, another pulse (delayed for 4ns with respect to the sampling one) which starts switching bottom plates of the binary-weighted caps from Vref=0.9V to GND. Switches turn on one by one with interval set by delay blocks - 2ns (allowing some transients). Bottom plate switches are assigned to have Ron=150Ohm. Even though the bridge cap is not set as a fraction as it is supposed to, I expect it to lead only to a constant gain error in conversion.
In the plot above with blue trace being the output voltage of the CDAC, one sees that after sampling switch opens the signal finds some discharge path, voltage does not settle on none of the caps until 5th bit and after this 5th bit it "jumps" back after the switch closes. I would like to hear suggestions why this does not work as one would expect to see in case of "causal" binary-weighted array without any shunting capacitor.
Thanks everyone in advance.
I am currently designing a fully-differential 12 bit SAR ADC using charge-scaling DAC. To reduce the total capacitance needed I have tried to investigate the behavior of such a split CDAC in MATLAB Simulink before going back to Spice and build it with the components from tech. library. When simulating split DAC I have noticed a behavior based on which one could have concluded that split CDAC concept can not be applied for my design.
Above you can see the setup: it uses L4M8-C structure emulating one side of the DAC with unit cap being 520fF based on matching and accuracy requirements, it samples input sinusoidal voltage with f=12MHz, Vcm=0.9V and V_ac=0.9V. When sampling switch turns off, another pulse (delayed for 4ns with respect to the sampling one) which starts switching bottom plates of the binary-weighted caps from Vref=0.9V to GND. Switches turn on one by one with interval set by delay blocks - 2ns (allowing some transients). Bottom plate switches are assigned to have Ron=150Ohm. Even though the bridge cap is not set as a fraction as it is supposed to, I expect it to lead only to a constant gain error in conversion.
In the plot above with blue trace being the output voltage of the CDAC, one sees that after sampling switch opens the signal finds some discharge path, voltage does not settle on none of the caps until 5th bit and after this 5th bit it "jumps" back after the switch closes. I would like to hear suggestions why this does not work as one would expect to see in case of "causal" binary-weighted array without any shunting capacitor.
Thanks everyone in advance.