Split Capacitor DAC, how to layout the split capacitor Cs?

[a991852]

Hi All,

I'm trying to implement a split capacitor array DAC, which is shown in this following picture:



The problem is that the scaling capacitor is not a unit sized capacitor, which cannot be placed inside the capacitor array.

My Idea for the solution is that:

If the scaling capacitor is 1.125C, then I'll put the 1C inside the capacitor array layout, and an external 0.125C. Hence I would get good matching for the 1C which is drawn with other unit sized capacitor, and the 0.125C even though with bad matching, 10% of 0.125C would not affect my circuit.

Does this idea seem applicable or is there another way?

 

[erikl]

Does this idea seem applicable or is there another way?

I think it's ok. But as you need a big array anyway, you could spend 8 more unit caps in series to achieve 0.125C - e.g. around the 1C scaling cap part - so you can build your whole scaling cap inside the array.

 

[a991852]

I think it's ok. But as you need a big array anyway, you could spend 8 more unit caps in series to achieve 0.125C - e.g. around the 1C scaling cap part - so you can build your whole scaling cap inside the array.

Thats a great idea too! Thanks!