Spinal HDL, Describe your digital hardware in Scala [WIP]

[dolu1990]

Hi,

We are in 2015, VHDL and Verilog are dinosaurs and don't give the possibility to build abstraction and to describe a complex generic design without pain.

Spinal HDL is a Scala internal domain specific language that try to increase productivity by some way :

• All the syntax of Scala is usable.
• Allow you to build abstraction, for example, you can describe the AXI bus, and then instantiate and connect it in one line. Goodbye endless declaration, wiring and mistake from it.
• No restriction to genericity, For example you can define a FIFO with a generic data type.
• Remove useless (for syntetisis) process/always syntax, you don't have to play with sensitivity list.
• ClockDomain, you don't need to wire it everywhere, it do it for you. You define clocking area, and all logic that is into use the clock. Additionally it checks cross clock domain violations.

Technically, the language is a Scala library that allows the user to describe his digital hardware by building into the PC memory a graph. Then this graph is flushed into VHDL (for the moment).

The project has a good advancement, the most of features are already functional :

• VHDL backend : The HDL is flushed into a synthesizable VHDL file
• Base Types : Bool, Bits, UInt, SInt, Enum
• Bundle : That allow you to describe a data structure with the possibility for each element to specify the direction (in,out). That is useful to describe bus.
• Vec : That allow you to create an array of data.
• BlackBox : Allow you to instantiate a third party HDL component.
• Conditional blocks and operators

We are now looking for motivated person to test, feedback and contribute to the language.

There is the git : https://github.com/SpinalHDL/SpinalCore

Have a nice week.