// Main circuit
//
// I/O nodes: agd1p8 dacout vdda vssa comn comp \
// agd1p8 dacout vdda vssa comn comp \
// I/O types: INP INP BID BID OUT OUT
//Comparator ON/OFF
//sw1 agd agd1p8 switch vclock=0 vclock=1
//sw2 dac dacout switch vclock=0 vclock=1
vcvs1 (d3 vssa) bsource v=1000*v(agd1p8, dacout) max_val=3.3 min_val=0 td=0.1u
m1 ( vssa d3 comnv vdda ) pmos w=1u l=0.35u m=1 ad=0.95p as=0.95p pd=2.9u \
ps=2.9u nrs=0.3 nrd=0.3
vcvs2 (d6 vssa) bsource v=1000*v(dacout, agd1p8) max_val=3.3 min_val=0 td=0.1u
m2 ( vssa d6 compv vdda ) pmos w=1u l=0.35u m=1 ad=0.95p as=0.95p pd=2.9u \
ps=2.9u nrs=0.3 nrd=0.3
//Invert clkc
//xs1 ( clkc clckp vdda vssa ) inm
//Comparator ON/OFF
//m3 ( agd clkc agd1p8 vdda ) pmos w=1u l=0.35u m=1 ad=0.95p as=0.95p pd=2.9u \
// ps=2.9u nrs=0.3 nrd=0.3
//m4 ( dac clkc dacout vdda ) pmos w=1u l=0.35u m=1 ad=0.95p as=0.95p pd=2.9u \
// ps=2.9u nrs=0.3 nrd=0.3
vcvs3 (comp vssa) bsource v=10*v(compv, vssa) max_val=3.3 min_val=0
vcvs4 (comn vssa) bsource v=10*v(comnv, vssa) max_val=3.3 min_val=0
subckt inm i zn vdda vssa
// pin label : i zn vsp vsn
// node type : INP OUT BID BID
m2 ( zn i vssa vss ) nmos w=1u l=0.35u m=1 ad=0.95p as=0.95p pd=2.9u ps=2.9u \
nrs=0.3 nrd=0.3
m1 ( zn i vdda vdda ) pmos w=2u l=0.35u m=1 ad=1.9p as=1.9p pd=3.9u ps=3.9u \
nrs=0.15 nrd=0.15
ends inm
//
simulator lang=spice
// No stimulic7n0.stim
vss vss 0
vdda vdda vssa 3.3
vssa vssa 0
//Clock from lat_contr
//vclkc clkc vssa pwl(0u 3.3 34.3099u 3.3 34.31u 0 34.315u 0 34.3151u 3.3 34.5099u 3.3 34.51u 0 34.515u 0 34.5151u 3.3 34.7099u 3.3 34.71u 0 34.715u 0 34.7151u 3.3 34.9099u 3.3 34.91u 0 34.915u 0 34.9151u 3.3 35.1099u 3.3 35.11u 0 35.115u 0 35.1151u 3.3 35.3099u 3.3 35.31u 0 35.315u 0 35.3151u 3.3 35.5099u 3.3 35.51u 0 35.515u 0 35.5151u 3.3 35.7099u 3.3 35.71u 0 35.715u 0 35.7151u 3.3 35.9099u 3.3 35.91u 0 35.915u 0 35.9151u 3.3 36.1099u 3.3 36.11u 0 36.115u 0 36.1151u 3.3 36.3099u 3.3 36.31u 0 36.315u 0 36.3151u 3.3 36.5099u 3.3 36.51u 0 36.515u 0 36.5151u 3.3 36.7099u 3.3 36.71u 0 36.715u 0 36.7151u 3.3 36.9099u 3.3 75u 3.3)
//Inverted clock from lat_contr
vclkc clkc vssa pwl(0u 0 34.3099u 0 34.31u 3.3 34.315u 3.3 34.3151u 0 34.5099u 0 34.51u 3.3 34.515u 3.3 34.5151u 0 34.7099u 0 34.71u 3.3 34.715u 3.3 34.7151u 0 34.9099u 0 34.91u 3.3 34.915u 3.3 34.9151u 0 35.1099u 0 35.11u 3.3 35.115u 3.3 35.1151u 0 35.3099u 0 35.31u 3.3 35.315u 3.3 35.3151u 0 35.5099u 0 35.51u 3.3 35.515u 3.3 35.5151u 0 35.7099u 0 35.71u 3.3 35.715u 3.3 35.7151u 0 35.9099u 0 35.91u 3.3 35.915u 3.3 35.9151u 0 36.1099u 0 36.11u 3.3 36.115u 3.3 36.1151u 0 36.3099u 0 36.31u 3.3 36.315u 3.3 36.3151u 0 36.5099u 0 36.51u 3.3 36.515u 3.3 36.5151u 0 36.7099u 0 36.71u 3.3 36.715u 3.3 36.7151u 0 36.9099u 0 75u 0)
vdacout dacout vssa pwl(30u 1.8 34.30u 1.8 34.31u 1.1 34.5u 1.1 34.51u 1.6 34.70u 1.6 34.71u 1.85 34.90u 1.85 34.91u 1.75 35.1u 1.75 35.11u 1.8 35.3u 1.8 35.31u 1.76 35.50u 1.76 35.51u 1.77 35.70u 1.77 35.71u 1.79 35.90u 1.79 35.91u 1.82 36.70u 1.82 36.71u 1.8 75u 1.8)
vagd1p8 agd1p8 vssa 1.8
//
simulator lang=spectre
// Library
include "/home/sola/cad/lib/spec/lib/xh035_lt.opt"
include "/home/sola/cad/lib/spec/lib/xh035_lt.scs" section=tm
op options save=selected currents=selected
//
tm tran start=34u stop=37u compression=yes errpreset=conservative
//
save clkc agd1p8 dacout comn comp \
// rext:currents vdda:currents pd clkc ckaz vrefp vrefn xs3.in1 xs3.ip1 xs3.op2 xs3.on2 xs3.w_15 xs3.w_16 xs3.on1 xs3.op1
// ttm_ alter param=temp value=-40
// tr_40 tran stop=65u compression=yes errpreset=conservative
// tr_25 tran stop=65u compression=yes errpreset=conservative
// ttm_125 alter param=temp value=125
// tr_125 tran stop=65u compression=yes errpreset=conservative