simon.harpham@ieee.org
Newbie level 4
The original files for the following are at:
**broken link removed**
I have repeated the netlist part here: - copy them into Notepad to view them properly. There is also a SIMetrix schematic version there that should run in the evaluation version ok.
Chrs, SimonH.
**broken link removed**
I have repeated the netlist part here: - copy them into Notepad to view them properly. There is also a SIMetrix schematic version there that should run in the evaluation version ok.
Chrs, SimonH.
Code:
***************************************************************************************
*** TL494_test.net [email]SimonLeSpicer@yahoo.com[/email] 30Apr2013 ***
***************************************************************************************
*** See: "TL494 PULSE-WIDTH-MODULATION CONTROL CIRCUITS" to be found at: ***
*** ***
*** [url]http://www.ti.com/lit/ds/symlink/tl494.pdf[/url] ***
*** ***
*** The Test circuit schematic is based on that in Figure 1 on page 6. ***
*** ***
***************************************************************************************
*/////// Formatted for Wordpad Formatted for Wordpad Formatted for Wordpad \\\\\\\***
***************************************************************************************
*** To run this deck open a "SIMetrix Command Shell" window (the one that opens ***
*** when you click on your SIMetrix desktop icon) then go to the "Simulator" drop ***
*** down menu then select "Run Netlist ..." (or you could type <Alt>+l, then n) ***
*** to open the "Script File" explorer window. Search for this file. Once you ***
*** have located it, double-click on it open. The simulation should run and plot ***
*** the Voltage Waveforms as in Figure 1 on page 6 of the TL494 Datasheet. To ***
*** see tham stacked as in Fig 1, select the "Curves" pull-down menu on the plot ***
*** window, then Stack All Curves. ***
*** ***
*** NOTE: You will need to alter the .inc line to point to where you have saved ***
*** the TL494.ckt sub-circuit file before running the simulation. Also see foot- ***
*** note at end of this file. ***
***************************************************************************************
*** Start the Testbench Netlist ***
***************************************************************************************
*** First, declare some parameters:
.param Vdc=15 ; Sets VCC
.param tr=5n tf={tr}
.param Fosc=10k ; not used in main circuit: sets up DTC and FB timing
.param Vth_DTC = 3.0 ; = typ, max = 3.3V
.param Vth_FB = 4.0 ; = typ, max = 4.5
*** then hookup the circuit:
X1 1IN+ 1IN- FB DTC CT RT GND C1
+ E1 E2 C2 VCC CTRL REF 2IN- 2IN+
+ TL494
Vsupply Vsupply 0 {Vdc}
Rsupply Vsupply VCC 1
Rgnd GND 0 0.01
R_C1 VCC C1 150 ; Output 1
R_C2 VCC C2 150 ; Output 2
R_E1 E1 GND 1 ; Testpoint 1
R_E2 E2 GND 1 ; Testpoint 2
R_1in+ 1IN+ 0 1K ; Sense input current
R_2in+ 2IN+ 0 1K ; Sense input current
R_ctrl CTRL REF 1
R_1in- 1IN- REF 1K ; Sense input current
R_2in- 2IN- REF 1K ; Sense input current
R_Rt RT 0 12K ; 12k sets Fosc to 10kHz, 1.5K < R_Rt < 500K
C_Ct CT 0 10n ; 10n sets Fosc to 10kHz, 470p < C_Ct < 10uF
R_DTC DTC TST1 1K ; Senses input current
R_FB FB TST2 1K ; Senses input current
*** set up the inputs:
V_DTC TST1 0 PWL ( 0 0 {9/Fosc} {1.1*Vth_DTC} {9/Fosc+tf} 0 )
V_FB TST2 0 PWL ( 0 0.7 {11/Fosc} 0.7 {19/Fosc} {1.1*Vth_FB} )
***************************************************************************************
*** and do a bit of housekeeping: - load sub-ckt file from the directory you placed
*** it in: (probably with this netlist)
.inc C:\Documents\IPcells\PWM\model\SIMetrix\TL494.ckt
*** set up the simulation deck:
*** run DC operating point to check everything OK:
* .op ; used for debug only.
*** then run the sim proper:
.tran 50n 2.2m 0 200n UIC
* .tran 50n 0.5m 0 200n UIC
*** and plot outputs:
.graph FB
.graph DTC
.graph CT
.graph C2
.graph C1
* .graph 1IN+
* .graph 1IN-
* .graph 2IN+
* .graph 2IN-
* .graph CTRL
* .graph E1
* .graph E1
* .graph REF
* .graph VCC
* .graph GND
* .graph TST1
* .graph TST2
***************************************************************************************
*** FOOTNOTE: The sub-circuit called implements an Hspice node controlled ***
*** resistor, so we need to add a file called DeviceConfig.sxdcf containing the ***
*** line: ***
*** ModelName=R,Level=0,Device=HspiceRes,Letter=R ***
*** to the ***
*** C:\Program Files (x86)\SIMetrixIntro560\support\ ***
*** and the ***
*** C:\Program Files (x86)\SIMetrix550\support\ ***
*** ***
*** directory paths to allow SIMetrix to handle that form of resistor definition. ***
*** ***
*** REMEMBER to close then re-open SIMetrix to enable the directive. ***
*** and to put a Carriage Return at end of line after the "R". ***
*** ***
*** This netlist should run OK under any of the evaluation versions. It has only ***
*** been checked on SIMetrix versions Micron A-D 5.40 and SIMetrix Simplis 5.50, ***
*** and 5.60. Other versions may need different patches to the netlists to get ***
*** them to run correctly. ***
***************************************************************************************
.END
*******************************************************************************************
*** TL494.ckt [email]SimonLeSpicer@yahoo.com[/email] 30Apr2013 ***
*******************************************************************************************
*** Original netlist appears at: ***
*** ***
*** [I]**broken link removed**[/I] ***
*** ***
*** Edited here by [email]SimonLeSpicer@yahoo.com[/email] for SIMetrix User Group and for its ***
*** members personal and private study only. Not to be used for fiscal gain. ***
*** ***
*******************************************************************************************
*** Formatted for Notepad Formatted for Notepad Formatted for Notepad ***
*******************************************************************************************
*** Changes made: ***
*** Pspice's $ replaced by SIMetrix's ; ***
*** Carriage return removed from end of .SUBCKT, E4 and E9 lines ***
*** Pin order re-arranged to match package ***
*** Nodes re-named to match pin names ***
*** G1 CT GND VALUE = {I(VOSS)} changed to: F1 CT GND VOSS 1 ***
*** VALUE = fn1 & fn2 changed to: VALUE = fn1 && fn2 ***
*** Oscillator section substantially re-written fo function in both SIMetrix ***
*** and Hspice - refer to inline annotation. ***
*******************************************************************************************
.SUBCKT TL494 1IN+ 1IN- FB DTC CT RT GND C1 E1 E2 C2 VCC CTRL REF 2in- 2in+
*******************************************************************************************
*** Old Oscillator Section ************************************************************
* G1 CT GND VALUE = {I(VOSS)}
* F1 CT GND VOSS 1
* Rk CT 9 { 10+1000*EXP(-V(CT)/0.4) }
* S1 9 2 CT GND SV2
* V4 GND 2 3
* S2 RT 15 CT GND SV8
* VOSS 15 GND 3
*** New Oscillator Section ************************************************************
Ein In 0 CT GND 1 ; connects input to CT for feedback from SRFF
RfixIn In 0 1e012 ; suppresses "singular supply" warning for E1
*** Set VHYS=2.9 to make f = 1/(Rt*Ct) set to 2.4 to centre on TL494 response.
*** Ensure VTHR-VHYS/2 > 0V and VTHR+VHYS/2 < Vdc
X1 In In Q QB GND SRFF VHYS=2.4 VTHR={VHYS/2+50m}
RfixQ Q 0 1e12 ; suppresses "1 connection at node 0:q" warning
RfixQB QB 0 1e12 ; suppresses "1 connection at node 0:qb" warning
VOSS 3V0 GND 3 ; biases RT to set up reference current
R_S2 RT 3V0 { 1e12*(1+((0.501-v(QB)) /( ((0.501-v(QB) )**2)**0.5 + 1e-12) ) + 1e-14 ) }
Fup GND CT VOSS -1 ; CCCS - charges CT
Rpd CT GND { 1e12*(1+((0.49-v(Q)) /( ((0.49-v(Q) )**2)**0.5 + 1e-12) ) + 1e-12 ) }
RDlmtP CT VCC { 1e12*(1+((-v(CT,VCC) )/( ((-v(CT,VCC) )**2)**0.5 + 1e-12)) + 1e-11 ) }
RDlmtN GND CT { 1e12*(1+((-v(GND,CT))/( ((-v(GND,CT) )**2)**0.5 + 1e-12)) + 1e-11 ) }
*******************************************************************************************
.SUBCKT SRFF S NR Q QB VSS VTHR=0.5 VHYS=0.1
*** ===================================================================================
*** NOTE: internal FF relys on delay through output buffers to hold previous state.
*** NSet input inverted to become a Set. NR and S thresholds have been altered to
*** become hysteretic inputs.
.param ron=2k roff=1G
RQi VSS Qi {ron*(1+(0.51-v(QB))/(ABS(0.51-v(QB))+ron/roff))}
IQi VSS Qi {1/(2*ron)}
CQi VSS Q 2p
RQBi VSS QBi {ron*(1+(0.51-v(Q) )/(ABS(0.51-v(Q) )+ron/roff))}
IQBi VSS QBi {1/(2*ron)}
CQBi VSS QB 2p
.param vSET=VTHR+VHYS/2 vRST=VTHR-VHYS/2
RS VSS QBi {roff*(1+(vSET-v(S) )/(ABS(vSET-v(S) )+100/roff))}
RR VSS Qi {roff*(1+(v(NR)-vRST)/(ABS(v(NR)-vRST)+100/roff))}
EQ OUT VSS Qi VSS 1
RQ OUT Q {ron}
EQB OUTB VSS QBi VSS 1
RQB OUTB QB {ron}
*** ===================================================================================
*** Debug hooks - "comment" out in final netlist:
* .nodeset Qi = 0 QBi =1
* .graph Q
* .graph QB
*** ===================================================================================
.ends SRFF
*******************************************************************************************
*** Return to the re-formatted but otherwise unaltered netlist: ***
*******************************************************************************************
*** Dead-Time Control Comparator ******************************************************
V6 16 DTC 0.12 ; offset DTC input
S4 DTM 23 CT 16 SV6 ; VON=1m VOFF=1m - compare DTC with CT
V8 23 GND 10 ; 10V source wrt GND = comparators' output via S4
R19 DTM GND 100 ; load V8 via S4
*** ===================================================================================
*** Debug hooks - "comment" out in final netlist:
* .graph DTM
*** ===================================================================================
*** Error Amplifiers ******************************************************************
R7 GND 1IN+ 500K
R8 GND 1IN- 500K
RE1 1IN+ 1IN- 1G ; added by E1
E1 7 GND TABLE {V(1IN+,1IN-)} = (0,0) (0.4M,4) (20M,5)
R11 11 7 100
C2 11 GND 200N
R14 Err1 11 150
C4 Err1 GND 100N
D1 Err1 FB GENERIC
R9 GND 2IN+ 500K
R10 GND 2IN- 500K
RE2 2IN+ 2IN- 1G ; added by E2
E2 8 GND TABLE {V(2IN+,2IN-)} = (0,0) (0.4M,4) (20M,5)
R12 12 8 100
C3 12 GND 200N
R15 Err2 12 150
C5 Err2 GND 100N
D2 Err2 FB GENERIC
I1 FB GND DC 0.7M AC 1 0 ; bias FB node
*** ===================================================================================
*** Debug only - "comment" out in final netlist:
* .graph FB
*** ===================================================================================
*** Pulse Width Modulator Comparator***************************************************
V7 20 CT 0.7 ; offset CT
S3 PWM DTM 20 FB SV6 ; compare CT with FB, gate DTM to PWM (= input CLK to PSFF)
R18 PWM GND 100 ; loads 10V source via S4 and S3, leads to Output S&H (below)
*** ===================================================================================
*** Debug only - "comment" out in final netlist:
* .graph PWM
*** ===================================================================================
*** Output Control ********************************************************************
*** This snippet uses a VCVS implementation of NAND gate only logic - for example:
*** E4 functions as a 3 input NAND gate thus:
***
*** VALUE=5-5*(IF E3_M2 > 0.8 AND PWM > 0.8 AND E8_M4 > 0.8 THEN 1 ELSE 0)
*** | | |
E4 28 GND VALUE = {5-5*((V(M2)>(V(GND)+0.8)) && (V(PWM)>(V(GND)+0.8)) && (V(M4)>(V(GND)+0.8)))}
R21 M3 28 400 ; M3 goes to the 1st Input of NAND2_E7
C7 M3 GND 20P ; and the 1st input to NAND2_E8 (both below)
*** ===================================================================================
*** The use of NAND only logic to implement the control function means that any
*** schematic drawn for this netlist will look very different to the schematic for this
*** same block as depicted in the datasheet or any application note dealing with the
*** TL494. The following nodes on the left of each equality:
***
*** PWM = C1 input to the Pulse-Steering Flip-Flop
*** M3 = 1D input (and QB output) to the Pulse-Steering Flip-Flop
*** not_M3 = Q output of the Pulse-Steering Flip-Flop
*** M6 = output of the upper AND gate leading to Q1
*** not_M6 = output of the lower AND gate
*** 40 = Q1's base
*** 39 - Q2's base
***
*** correlate to the right hand nodes, which may be found in the Functional Block
*** Diagram on page 2 of the Datasheet.
*** ===================================================================================
*** Debug only - "comment" out in final netlist:
* .graph M3
* .graph M6
* .graph 39
* .graph 40
*** ===================================================================================
*** E7, E6, E8, E5 and E3 are examples of a 2 input NAND gate implementation:
E7 36 GND VALUE = {5-5*((V(M3)>(V(GND)+0.8)) && (V(M5)>(V(GND)+0.8)))} ; =5*(1-(IF E4_M3>0.8 AND E6_M5>0.8 THEN 1 ELSE 0))
R26 M6 36 400
R29 GND M6 10K ; M6 feeds into 2nd input of NAND2_E6
C10 M6 GND 20P ; and to 2nd Input of NAND2_E8 (both below)
R30 40 M6 1K
S9 GND 40 CTRL GND SV7 ; Clamps M6, Node 40 outputs to Q1 via S6 (near end, below)
E6 34 GND VALUE = {5-5*((V(M2)>(V(GND)+0.8)) && (V(M6)>(V(GND)+0.8)))} ; =5*(1-(IF E3_M2>0.8 AND E7_M6>0.8 THEN 1 ELSE 0))
R25 M5 34 400
S8 GND 39 CTRL GND SV7
R28 39 M5 1K ; M5 feeds into 2nd input to NAND2_E7 (above)
C9 M5 GND 20P ; only
E8 38 GND VALUE = {5-5*((V(M3)>(V(GND)+0.8)) && (V(M6)>(V(GND)+0.8)))} ; =5*(1-(IF M3>0.8 AND M6>0.8 THEN 1 ELSE 0))
R27 M4 38 400 ; M4 feeds into 1st input to NAND2_E5 (below)
C11 M4 GND 20P ; and 3rd input of NAND3_E4 (above)
E5 30 GND VALUE = {5-5*((V(M4)>(V(GND)+0.8)) && (V(M2)>(V(GND)+0.8)))} ; =5*(1-(IF M4>0.8 AND M2>0.8 THEN 1 ELSE 0))
R22 M1 30 400 ; M1 feeds into 1st input to NAND3_E3 (below)
C8 M1 GND 20P ; only
E3 26 GND VALUE = {5-5*((V(M1)>(V(GND)+0.8)) && (V(PWM)>(V(GND)+0.8)))} ; =5*(1-(IF M1>0.8 AND PWM>0.8 THEN 1 ELSE 0))
R20 M2 26 400 ; M2 feeds into 1st input to NAND3_E4 (above)
C6 M2 GND 20P ; only
*** Output S&H ************************************************************************
R23 31 PWM 1K ; PWM bypass to S&H on output devices Q1 and Q2
C12 31 40 20P ; Q1 input = S&H gated by M6 (below)
S6 C1 42 31 40 SV1 ; connects C1 via D3 to E1, on > 7V1, off < 7V0
D3 42 E1 GENERIC ; Q1e
C13 31 39 20P ; Q2 input = S&H gated by M5 (below)
S7 C2 44 31 39 SV1 ; connects C2 via D4 to E2, on > 7V1, off < 7V0
D4 44 E2 GENERIC2 ; Q2e
*** ===================================================================================
*** Debug only - "comment" out in final netlist:
* .graph C1
* .graph C2
* .graph E1
* .graph E2
*** Reference and Supply **************************************************************
E9 REF GND VALUE = {5*(V(VCC,GND)>=6)+(V(VCC,GND)-1)*(V(VCC,GND)<6)*(V(VCC,GND)>1)}
R24 GND REF 100K
R17 VCC GND 1K
S5 GND 20 VCC GND SV3 ; clamps PWM off (by pulling CT to 0.7V) if VCC<6.9V
*******************************************************************************************
*******************************************************************************************
*** Define Models NOTE: SV2 and SV8 are not unused in final netlist
*******************************************************************************************
.MODEL SV1 VSWITCH (RON=10 VON=7.1 VOFF=7 )
* .MODEL SV2 VSWITCH ( VT =1.48 VH=1.49 ) ; unused
.MODEL SV3 VSWITCH ( VON=6.9 VOFF=7 )
.MODEL SV6 VSWITCH ( VON=0.001 )
.MODEL SV7 VSWITCH ( VOFF=3.1 VON=3 )
* .MODEL SV8 VSWITCH (ROFF=100MEG VT =3 VH=-0.1 ) ; unused
.MODEL GENERIC D (BV=500 CJO=2.5P IS=8N M=100M N=2 RS=400M TT=1N VJ=700M)
.MODEL GENERIC2 D (BV=500 CJO=2.5P IS=30N M=100M N=3.2 RS=4M TT=1N VJ=400M)
*******************************************************************************************
.ENDS TL494
*******************************************************************************************
*** NOTE: This sub-circuit uses the Hspice node controlled resistor so we need to ***
*** add a file called DeviceConfig.sxdcf containing the line: ***
*** ***
*** ModelName=R,Level=0,Device=HspiceRes,Letter=R ***
*** to the ***
*** C:\Program Files (x86)\SIMetrixIntro560\support\ ***
*** and the ***
*** C:\Program Files (x86)\SIMetrix550\support\ ***
*** ***
*** directory paths to allow SIMetrix to handle that form of resistor definition. ***
*** ***
*** REMEMBER to close then re-open SIMetrix to enable the directive. ***
*** and to put a Carriage Return at end of line after the "R". ***
*** ***
*** This netlist should run OK under any of the evaluation versions. It has only ***
*** been checked on SIMetrix versions Micron A-D 5.40 and SIMetrix Simplis 5.50, ***
*** and 5.60. Other versions may need different patches to the netlists to get ***
*** them to run correctly. ***
*** ***
*** To run this deck open a "SIMetrix Command Shell" window (the one that opens ***
*** when you run SIMetrix) then go to the "Simulator" drop down menu then select ***
*** "Run Netlist ..." (or you could type <Alt>+l, then n) to open the "Script ***
*** File" explorer window, then search for this file. Once you have found it, ***
*** select it then click on [Open]. The simulation should run and plot. ***
*** ***
*******************************************************************************************
*** TL494.ckt [email]SimonLeSpicer@yahoo.com[/email] 30Apr2013 ***
*******************************************************************************************