Hi, I found it strange to have "backend" interface for a SPI master verilog code. Could anyone comment about its necessity in simulation or formal verification ?
For actual hardware testing, I do not think it is necessary to write a backend interface when the slave itself is a SPI flash since the flash already had this backend interface internally.
However for simulation, I believe this backend interface is still needed ??
I have included the backend interface for the master (FPGA) flash controller.
However, I am not sure how to simulate this correctly ? There is no physical SPI flash that I can simulate with in computer. Do I really need a verilog simulation model of the SPI flash device itself ?
My Winbond W25Q32FV SPI flash **broken link removed** that I can use
module SPI(clk, reset, data_valid, data_MOSI, data_ready, data_MISO, MISO, MOSI, clk_flash, CS_flash);parameter MOSI_DATA_BITWIDTH =8;parameter MISO_DATA_BITWIDTH =8;input clk, reset;input data_valid;input[MOSI_DATA_BITWIDTH-1:0] data_MOSI;// data going into the slave (SPI flash)outputreg data_ready;outputreg[MISO_DATA_BITWIDTH-1:0] data_MISO;// data originating from slave (SPI flash)input MISO;outputreg MOSI;output clk_flash;outputreg CS_flash;reg[($clog2(MISO_DATA_BITWIDTH)-1):0] in_index;reg[($clog2(MOSI_DATA_BITWIDTH)-1):0] out_index;assign clk_flash = clk;always@(posedge clk)beginif(reset)begin
CS_flash <=1;endelsebeginif(data_valid) CS_flash <=0;// new SPI flash transactionelse CS_flash <=1;// SPI flash transaction finishedendendalways@(posedge clk)beginif(reset)begin
MOSI <=1;
out_index <=0;endelsebegin
MOSI <= data_MOSI[out_index];
out_index <= out_index +1;endendalways@(negedge clk)// this SPI flash sends out its data on the falling edge, so this flash controller has to follow SPI flash specbeginif(reset)begin
data_ready <=0;
data_MISO <=0;// all zeroes
in_index <=0;// the shift register 'data_MISO' stores the data starting from LSBendelsebeginif(in_index == MISO_DATA_BITWIDTH)begin
data_ready <=1;// data collection from slave is complete or finished now
in_index <=0;endelsebegin
data_ready <=0;if(CS_flash &&!data_ready)begin// collect data from slave (SPI flash) during the transaction
data_MISO[in_index]<= MISO;
in_index <= in_index +1;endendendendendmodule