Yes I agree, but I've also checked the simulation under "free runing option" (where FPGA is operating asynchronously to the Simulink simulation) and got the same answers...
Thank You but I don't understand. In first sim I change SDI during high SCL, but in the second I change it during low SCL and the answer was still wrong. Maybe You are thought aboutt CLK system clock?
Nope. When I said SCL I meant SCL the SPI clock, not your system clock.
I tried to modify SCL wave and I take something like this:
View attachment 79131
Well, that is still wrong, since you are still changing the SDI data when SCL is high. You should be changing SDI when SCL is low.
Im not sure bo I think the answer is "11000111", but it still inst Who Am I Answer
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I really don't understand differences between this two answers:
View attachment 79132
View attachment 79133
The first bit starts at falling edge of SCL after the CS is low in both examples... :/ And the answer is different
WTF are you doing?
Ahem, sorry. In the last one you start too soon fiddling with SDI.
SCL high is your idle state. CS high is your idle state.
Then you FIRST have CS go low to tell the SPI slave data is coming sooooon.
Then you have SCL go low so you can set SDI to your first bit of data.
And ONLY then do you start fiddling with SDI. So only after you have set SCL low for the first time can you set SDI to your first bit of data, a '1' in this case.
If that is still unclear, post your testbench + code. Hell, just zip up the archive and post it, and I'll take a look at it if you want. Saves a lot of back and forth.
Edit: Oh yeah, almost forgot to ask. Is this in real hardware with jtag and such? Or is this purely simulation? If it is purely simulation, then what are you using for the L3G4200D spi slave? The reason I ask, if you have testbench code for the L3G4200D then that is an additional source of potential errors.
Anyways, post code and/or project dirs.