SPI programming - rising/falling edge of clock

[luckyvictor]

Hi

I am new to program, and I don't know what I should do with the following configuration of my slave.

In my slave device:

DIN: latches data on DIN on the falling edge of SCLK

DOUT: shifted out on rising edge of SCLK

so what does it mean of the clock when I set up my master device please?

 

[horace1]

when you configure the SPI interface you set it up to meet the requirements of the slave, e.g. this is part of the initialisation of a FM33256 RTC/SRAM attached to a PIC24FJ256GB110

// peripheral configurations
#define SPI_MASTER  0x0120      // select 8-bit master mode, CKE=1, CKP=0
#define SPI_ENABLE      0x8000    // enable SPI port, clear status

// initialise the FM33256 memory/RTC device
void FM33256init(void)
{
    unsigned char  Seconds,Minutes,Hours,Date,Month,Year;
    printf("\nFM33256 initialisation\n");
    // Set IOs directions for EEPROM SPI
    FM33256_CS_PORT = 1;		// set CS high (disable)
    FM33256_CS_TRIS = 0;		// set CS pin as output
    // set up pin mapping!
	_RP2R  = 8;			// map RP2 (pin 68) to output function 8 SPI1 CLK OUT
	_RP4R  = 7;			// map RP4 (pin 69) to output function 7 SPI1 DATA OUT
	_SDI1R   = 3;			// map SDI1 input to RP3 (pin 70)
    IFS0bits.SPI1IF = 0;        // clear interrupt flag
    SPI1CON1 = SPI_MASTER;  // select mode
    SPI1STAT = SPI_ENABLE;  // enable the peripheral

 

[ctownsend]

looks like the device uses SPI mode 1.
Serial Peripheral Interface Bus - Wikipedia, the free encyclopedia

 

[luckyvictor]

I have read this, but there is no clear instruction describing the configuration.

My slave is ADS1298, which is DIN: latches data on DIN on the falling edge of SCLK and DOUT: shifted out on rising edge of SCLK. My master is MSP430F2274, however, there is no detail describing how the data are shifted in and out from this micro controller. All it says is the SPI configuration registers, so I wonder to setup the SPI transmission, do i need to know only the SPI slave behaviour?? or it is necessary to know the behaviour of data shift IN/OUT for both the master and slave??

 

[Embedded Partner]

i MSP430 of SPI module , you must sellect the SPI according to ADS1298.....
check the clock/timing diagrams of SPi module you get to know

 

[luckyvictor]

so it means I only need to know how my slave works in SPI? but I don't need to care how my master clock in/out the data?

 

[FvM]

Refer to the respective MSP430 family user's guide. The SPI mode is selected by setting clock phase and polarity in the transmit control register. Default CKPH=0 and CKPL=0 means SPI mode 1, as needed for the ADS1298.

 

[Embedded Partner]

SPI protocol will be same for all the devices
i mean if your slave and master both are having SPI protocol that mean that there is a standard for communicating between those devices(that is SPI protocol)...

if your slave DIN:latches data on falling edge and Dout: send's data on rising edge(which is SPI protocol)
then you need to select SPI configurations in the master as similar as above

 

[Embedded Partner]

for more reference on SPI
refer these 2 diagrams thats enough