amnakhan786
Junior Member level 3
I AM INTERFACING ADE7758 WITH AVR THROUGH SPI.WITH Fosc=22 MHZ, SCL=1.375 MHZ,. THE DATASHEET SAYS:
[u]When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use.
THE DATA IN ADE7758 IS IN THE FORM OF 24 BIT REGISTERS.WONT THE LAST TWO BYTES WILL BE LOST IF CLOCK GENERATOR STOPS JUST AFTER SHIFTING ONE BYTE.
CAN SENDING A DUMMY BYTE RESOLVE THIS ISSUE.BUT HOW I CAN DO THAT?
[u]When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use.
THE DATA IN ADE7758 IS IN THE FORM OF 24 BIT REGISTERS.WONT THE LAST TWO BYTES WILL BE LOST IF CLOCK GENERATOR STOPS JUST AFTER SHIFTING ONE BYTE.
CAN SENDING A DUMMY BYTE RESOLVE THIS ISSUE.BUT HOW I CAN DO THAT?