Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Speeding up ModelSim simulation

Status
Not open for further replies.

matrixofdynamism

Advanced Member level 2
Joined
Apr 17, 2011
Messages
593
Helped
24
Reputation
48
Reaction score
23
Trophy points
1,298
Activity points
7,681
If ModelSim has to fill in a wave window, a simulation takes longer as the necessary data is logged into memory rather than discarded. Therefore, to speed up simulation once a wave window has been open and simulation started, is it sufficient to close the wave window midway and the simulation will not save those signals anymore, making the simulation faster?
 

Nope, that wont work, as you've asked it to log all the signals. There are no ways to speed it up once simulation has started.
Other things to try and speed up simulation:
1. Get a faster machine
2. Use optimisations (ie. dont use -novopt)
3. Only log what you need to look at.
4. Make a self checking testbench and run in batch mode (ie. no wave window).
5. Use the 32 bit version (at least, this used to be the case a few years ago - and mentor would even tell you this)
6. Use the code/memory profiler to see which part of the design are slowing the simulation down - try and understand why and if the code can be optimised
7. Use more behavioural code in your testbench (VHDL or SV).
 

Could you kindly elaborate on point 3?

Do you confirm that if I do not add signals to the wave window the simulation shall run faster?
 

It might run faster, but not by much. but what counts is whats on the wave window when you start the simulation. After it has started removing signals still means they are logged until the simulation is restarted (I think).

Either way - it wont make a lot of difference. if you were logging every signal in a large design (1000s of signals) cutting it down to a single entity may increase speed by a few %. The speed is mostly dictated by the code.
 

In my experience optimization of blocks you aren't interested in and enable only the visibility into what you are interested in (for the block you are looking at) will significantly improve the simulation performance.

For most designs simulation performance isn't critical, unless you plan on running simulations that are seconds of real time.

Also having the wave window showing on the screen and updating (cursor at the end of the simulation where it's updating) seems to slow the simulation down, based on having timed simulations with a stopwatch. I usually either a) minimize the wave window, b) move the cursor to somewhere else in the waveform so the wave window doesn't update and scroll. I noticed this even on a 8 core system, so it appears it's not doing a good job of using multiple processors.
 

In case of VHDL - using "bit" instead of "std_logic" (whenever possible) can speed things up...
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top