Speech Recognition VHDL

[tarang]

vhdl speech recognition

Hey Guys, VHDL HELP

I am a beginner to VHDL. I know how to write basic codes in VHDL.
I want to implement a Speech Recognition system using FPGA. So i want to learn how to design the code in VHDL.
For that i have to learn the very basic of Signal Processing or Analyzing using small inputs.

Can anyone give me start to it? PLEASE

thanx in adv

 

[hananeel]

speech recognition using vhdl

well, matlab has capabilities to work with HDL , in fact you can star to design filters, and then converting to vhdl code, these a list a software that i use:

xilinx ISE 9.2
matlab r2007a
system generator
acceldsp
active HDL 7.3
orcad 16.0

look for each one of them and learn how to use them , u can combine them to achive from basic to very complex aplications on vhdl, ... well.. c ya !

 

[tarang]

speech recognition vhdl

Thanx for the reply....it gave me a good starting point....

I have seen everyone talking about filters.
For out initial design we will use the
- DSP micro controller to process the incoming analog siganl. It will
filter and sample the signal to digital.
- Then the software stored in the uC will frame and window the
digitized the signal.
- This will then be passed on to the FPGA which will start comparing
the words using HMM.

Do i still have to implement the filters in FPGA? can i directly take the data from, lets say SRAM (where uC will store the processed digital signal) and use it compare?

That is how i have designed the system so far. Can anyone comment on this design, give some views....

thanx