specify in verilog not working in questasim

[gck]

Hi all,

I am trying to simulate the following program in questasim 6.5, for d ff model. I am getting setup and hold time violation but not the delay in output q.

Please suggest changes in code.

Thanks in advance

//D-FF model
module d_ff_model ( output reg q,
input d, clk, rst);

reg set_violation, hold_violation;

initial
$monitor("set_violation= %d , hold_violation=%d", set_violation , hold_violation);

always @(rst, posedge clk)
begin
if(rst)
q <= 'b0;
else
q <= d;
end

//Specify block for defining delays
specify
// propogation delay
// High to Low and Low to High
specparam t_h_l = 50, t_l_h = 15;
(posedge clk => (q:d) ) =(t_h_l, t_l_h);
(rst *> q) = (t_h_l, t_l_h);


//setup time 10 ns
specparam t_setup = 10;
$setup(d, posedge clk &&& (~rst), t_setup, set_violation ) ;

//Hold time 5 ns
specparam t_hold = 5;
$hold(posedge clk &&& (~rst), d, t_hold, hold_violation);

endspecify
endmodule // d_ff_model