Special adder in VHDL

[MahmoudHassan]

i need to design adder 8 bit so that if the addition of the two numbers is larger than 255 then the output is 255
if less than 255 then the output is the sum
my design is to take the carry output into multiplexer 's select so that if carry =1 select "11111111" and if carry =0 output is the sum

but simulation is wrong any help

the vhdl code

library ieee;
use ieee.std_logic_1164.all;

entity sai_add is
--generic ( n:natural:=8);
port( a,b:in std_logic_vector (7 downto 0);
cin : in std_logic;
--cout : out std_logic;
z : out std_logic_vector (7 downto 0));
end sai_add;

architecture struct of sai_add is
component adder
generic (n : natural :=8);
port( A,B : in std_logic_vector (n-1 downto 0);
sum : out std_logic_vector (n-1 downto 0);
cin : std_logic;
cout : out std_logic);

end component;

signal temp1:std_logic;
signal temp2,temp3,temp4,temp5 : std_logic_vector (7 downto 0);

begin

L:adder
generic map (n=>8)
port map (A,B,temp2,cin,temp1);

--temp1 <= cout ;
temp5<= temp2 and not(temp1&"1111111");
temp3<="11111111";
temp4<= (temp1 & "1111111") and temp3;
z<= temp4 or temp5;

end struct;


===================================Adder component

library ieee;
use ieee.std_logic_1164.all;

entity adder is
generic (n : natural :=8);
port( A,B : in std_logic_vector (n-1 downto 0);
sum : out std_logic_vector (n-1 downto 0);
cin : std_logic;
cout : out std_logic);

end adder;

architecture struct of adder is

component fulladder
port (A,B,C:in std_logic;sum,carry_outut std_logic);
end component;

signal temp : std_logic_vector ( n downto 0);

begin
cout <= temp;
temp(0) <= cin;

la:for i in n-1 downto 0 generate
fa:fulladder port map (A(i),B(i),temp(i),sum(i),temp(i+1));
end generate;
end struct;

=================== the complete project in the attached files it programed on max Plus in the attached files

 

[TrickyDicky]

That seems very complicated. You could do it all in 32 lines of VHDL:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder_with_saturation is
  port (
    a,b : in unsigned(7 downto 0);
    cin : in std_logic;
    
    z   : out unsigned(7 downto 0)
  );
end entity adder_with_saturation;
  
architecture rtl of adder_with_saturation is
begin
  
  process(a, b, cin)
    variable temp_op : unsigned(8 downto 0);
  begin
    
    temp_op := ('0' & a) + ('0' & b) + unsigned'(x"00" & cin);
    
    if temp_op > 255 then
      z <= to_unsigned(255, 8);
      
    else
      z <= temp_op(7 downto 0);
    end if;
    
  end process;

end architecture rtl;

 

[MahmoudHassan]

can you design it structural not RTL ?
thanks