Derived Constraint Report
Derived Constraints for Inst_mem_wrapper/u_mem32/memc3_infrastructure_inst/sys_clk_ibufg
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|Inst_mem_wrapper/u_mem32/memc3_| 10.000ns| 3.334ns| 17.652ns| 0| 1| 0| 19616|
|infrastructure_inst/sys_clk_ibu| | | | | | | |
|fg | | | | | | | |
| Inst_mem_wrapper/u_mem32/memc3| 10.000ns| 0.952ns| 1.499ns| 0| 0| 0| 0|
| _infrastructure_inst/clk_2x_0 | | | | | | | |
| Inst_mem_wrapper/u_mem32/c3_s| 10.000ns| 1.499ns| N/A| 0| 0| 0| 0|
| ysclk_2x | | | | | | | |
| Inst_mem_wrapper/u_mem32/memc3| 10.000ns| 0.952ns| 1.499ns| 0| 0| 0| 0|
| _infrastructure_inst/clk_2x_18| | | | | | | |
| 0 | | | | | | | |
| Inst_mem_wrapper/u_mem32/c3_s| 10.000ns| 1.499ns| N/A| 0| 0| 0| 0|
| ysclk_2x_180 | | | | | | | |
| Inst_mem_wrapper/u_mem32/memc3| 13.333ns| 23.536ns| N/A| 1| 0| 19616| 0|
| _infrastructure_inst/mcb_drp_c| | | | | | | |
| lk_bufg_in | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk_50
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_50 | 7.852| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 1 Score: 1275 (Setup/Max: 1275, Hold: 0)
Constraints cover 19616 paths, 0 nets, and 2128 connections
Design statistics:
Minimum period: 23.536ns{1} (Maximum frequency: 42.488MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Aug 15 17:15:56 2018
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 202 MB