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Vref need not always be connected. Only when you add a watch dog circuit or a battery. the conntection method of VCCO is shown on every kind of FPGA's datasheet. You can search it carefully.
Vcco is the voltage that the IO pins of a specific bank use. For example, if you use PCI 3.3V, you set Vcco to 3.3V.
Vref is used in some IO standards. It is used as a threshold between a '0' and '1'. The FPGA have a differential amplifier at input, and Vref goes to one input, so when a specific IO on than bank goes below Vref, the FPGA see a 0. When the IO input goes over that Vref threshold, the FPGA see a 1.
Vref is not used for all the IO standards, but the biggest rules are:
- You can only have one voltage lever per bank. For example, you can mix LVCMOS 3.3V and LVTTL 3.3V, but you could not use a 2.5V standard if you also use 3.3V standard. This apply as a 'per bank' basis (most Xilinx have 8 banks, most @ltera have 4).
- Similarely, you can only use one Vref voltage lever standard per bank. The Vref must be set according to the standard. This is detailed in the electrical datasheets.
- If no IO use a standard that need a Vref, then all the Vref pins can be used as independent user IO. If you have one or more IO standard that need a Vref, then ALL the Vref of that bank must be connected to a voltage described by that standard, and Vref pins of that bank can NOT be used as IO.
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