Fish4Fun
Junior Member level 1
spartan ii vs spartan iii
Ok, I have searched the archives and I can’t seem to find much discussion about the advantages/disadvantages of the Xilinx Spartan-II vs the Spartan-3. I have read through the documentation of both devices and am left a bit more confused than when I started. I will briefly outline the two operational modes the FPGA will be used for in this project, and then point out what I see as apparent advantages of each device and hope that some of you with more experience can guide me to the proper device selection.
Operational Mode I will simply take 8 bit data from an ADC, buffer it onto a 16 bit register and then output it to a 16 bit external FIFO. The ADC’s maximum sample rate is 250MSPS, but the project parameters only require a maximum acquisition rate of ~180MSPS. The ability to utilize the 250MSPS rate of the ADC would be considered a “plus”, but not a requirement.
Operational Mode II uses the same ADC input, but requires transforming a number of the samples into a “period” Max, Min and Average. The 3 bytes per period then need to be compared to historical samples to derive a “pass/fail” output with a time reference output to the same external FIFO. This mode also requires loading and buffering historical samples.
My perception of the requirements of the FPGA seems to indicate the Spartan-II is the best choice for this project. This is based on the variety of I/O requirements of the various external components. The ADC output is LVDS_1.8, which neither device supports as a native I/O mode and thus will require an external converter or level shifter. The selected FIFOs are 3.3V logic. The external MCU I/O and some other interface logic is 5V which the Spartan-II supports, but the Spartan-3 does not. The Spartan-3 appears to have speed advantages over the Spartan-II; however, these are difficult to ascertain because the Spartan-3 appears to this reader to be somewhat ambiguous about actual performance speeds whereas the Spartan-II claims repeatedly to support system clock speeds to 200Mhz (well within the 180MSPS acquisition rate requirement). The Spartan-3 has dedicated multipliers, but these can only be considered a “bonus for future development” as they are not needed in the current synthesis.
The cost of the FPGA is, within reason, trivial, so the decision boils down to performance of the Spartan-3 over the Spartan-II VS the added complication of externally buffering all of the I/O devices except the FIFOs (which both devices support). I would really like to hear some first hand accounts of the Spartan-3 performance improvements over the Spartan-II. I would also be interested in any arguments for migrating toward a member of the Virtex series given the stated parameters.
Thanks in advance,
Fish
Ok, I have searched the archives and I can’t seem to find much discussion about the advantages/disadvantages of the Xilinx Spartan-II vs the Spartan-3. I have read through the documentation of both devices and am left a bit more confused than when I started. I will briefly outline the two operational modes the FPGA will be used for in this project, and then point out what I see as apparent advantages of each device and hope that some of you with more experience can guide me to the proper device selection.
Operational Mode I will simply take 8 bit data from an ADC, buffer it onto a 16 bit register and then output it to a 16 bit external FIFO. The ADC’s maximum sample rate is 250MSPS, but the project parameters only require a maximum acquisition rate of ~180MSPS. The ability to utilize the 250MSPS rate of the ADC would be considered a “plus”, but not a requirement.
Operational Mode II uses the same ADC input, but requires transforming a number of the samples into a “period” Max, Min and Average. The 3 bytes per period then need to be compared to historical samples to derive a “pass/fail” output with a time reference output to the same external FIFO. This mode also requires loading and buffering historical samples.
My perception of the requirements of the FPGA seems to indicate the Spartan-II is the best choice for this project. This is based on the variety of I/O requirements of the various external components. The ADC output is LVDS_1.8, which neither device supports as a native I/O mode and thus will require an external converter or level shifter. The selected FIFOs are 3.3V logic. The external MCU I/O and some other interface logic is 5V which the Spartan-II supports, but the Spartan-3 does not. The Spartan-3 appears to have speed advantages over the Spartan-II; however, these are difficult to ascertain because the Spartan-3 appears to this reader to be somewhat ambiguous about actual performance speeds whereas the Spartan-II claims repeatedly to support system clock speeds to 200Mhz (well within the 180MSPS acquisition rate requirement). The Spartan-3 has dedicated multipliers, but these can only be considered a “bonus for future development” as they are not needed in the current synthesis.
The cost of the FPGA is, within reason, trivial, so the decision boils down to performance of the Spartan-3 over the Spartan-II VS the added complication of externally buffering all of the I/O devices except the FIFOs (which both devices support). I would really like to hear some first hand accounts of the Spartan-3 performance improvements over the Spartan-II. I would also be interested in any arguments for migrating toward a member of the Virtex series given the stated parameters.
Thanks in advance,
Fish
