Spartan-6 GTP Phase-Alig​nment.

[YHubert]

Hello,

I'm working on a XC6LX75T.

I want to phase-align the 4 TX lanes of the 2 bottom GTP_DUAL_Tiles (X0Y0 and X1Y0).

I use one clock reference connected to one of the MGTREFCLK inputs.Using REFCLKPLL0, I can feed the adjacent GTP_DUAL through the CLKINEAST/WEST (UG386 - p40).

TX Phase alignment is "performed to match/adjust the phase difference between the PMA Parallel CLK Domain (XCLK) and the PCS Parallel CLK Domain (TXUSERCLK)".

What are the clocks part of the XCLK?

I understand p86 of UG386 is more or less how I need to distribute the timing signals.

If both lanes of a GTP_DUAL share the same TX PMA clock domain as suggested by the figure, I can understand both lanes are aligned. But how can I ensure the alignment with the other lanes of the second GTP_DUAL_Tile?

I'm actually a bit confused between "Phase-Alignment of PMA and PCS Clock domains" and "Phase-Alignment of TX Lanes"...

Could anyone give me some global summary of the alignment process for 4 TX Lanes?

Thx,

YH.

 

[permute]

Typically, some of the clocks can be passed through multiple GTP's with some restrictions. Channel bonding may also be relevant, depending on what you are trying to do.