spartan 6 FPGA + DDR2

[GhostInABox]

I am considering designing a spartan 6 + DDR 2 board and wondering if we need to run signal integrity checks for the PCB ?. or are following the guidelines going to be sufficient ?

I am pretty new to high speed design and hope to use Altium , I want to know if I need to know the board manufacturer specific PCB parameters for SI checks

Please let me know if anyone has any experience/thoughts about this

 

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I am considering designing a spartan 6 + DDR 2 board and wondering if we need to run signal integrity checks for the PCB ?. or are following the guidelines going to be sufficient ?

I am pretty new to high speed design and hope to use Altium , I want to know if I need to know the board manufacturer specific PCB parameters for SI checks

Please let me know if anyone has any experience/thoughts about this

Depends on your risk aversion.
From highest to lowest risk.
1. Arbitrarily pick pins on the part and cross your fingers.
2. Let the tools help you pick the pins, but put the RAM 10 inches away from the FPGA
3. Let the tools help pick the pins, place RAM <1 inch from the FPGA with no termination
4. Let the tools pick the pins, place RAM < 1 inch from the FPGA with correct termination
5. Tools pick pins, RAM < 1" away, SI done without using PCB parameters (stackup, dialectric)
6. Tool picks pins, RAM < 1" away, SI done using stackup, dialectric, vias modeled, etc.
7. ....instead of SI using a 3D magnetic field simulation...

As you can see the more accurate you want the simulation and the more risk adverse you are to be the more effort you'll expend. I've done #3 plus SI with stackup, dialectric, via, etc all included. The design worked perfectly and the signals were verified using a 2GHz high speed scope with active probes. Signals looked clean, even without the termination (board was too dense to include the termination, we did try and ended up removing them).

 

[GhostInABox]

Depends on your risk aversion.
From highest to lowest risk.
1. Arbitrarily pick pins on the part and cross your fingers.
2. Let the tools help you pick the pins, but put the RAM 10 inches away from the FPGA
3. Let the tools help pick the pins, place RAM <1 inch from the FPGA with no termination
4. Let the tools pick the pins, place RAM < 1 inch from the FPGA with correct termination
5. Tools pick pins, RAM < 1" away, SI done without using PCB parameters (stackup, dialectric)
6. Tool picks pins, RAM < 1" away, SI done using stackup, dialectric, vias modeled, etc.
7. ....instead of SI using a 3D magnetic field simulation...

As you can see the more accurate you want the simulation and the more risk adverse you are to be the more effort you'll expend. I've done #3 plus SI with stackup, dialectric, via, etc all included. The design worked perfectly and the signals were verified using a 2GHz high speed scope with active probes. Signals looked clean, even without the termination (board was too dense to include the termination, we did try and ended up removing them).

Thanks for your reply. I would like to know what tools was used for the project ?.. and would like to know if this kind of project is feasible as a hobby undertaking ?

 

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Mentor Hyperlinks. Very expensive EDA tool not really something a hobbyist would use.

Just make sure you use termination on all the lines and keep the RAM(s) close to the FPGA. Also try to keep the trace lengths matched per byte lane.