Spartan 3e (xilinx) \ fpga

[beapp]

Hey! i'm doing a project in spartan 3e using fpga! i'm really trying to do a clock but i can't do it ...i don't know even how too start.. =( somebody know how to do a clock using fpga ?? tks !

 

[mrflibble]

Hey! i'm doing a project in spartan 3e using fpga! i'm really trying to do a clock but i can't do it ...i don't know even how too start..

Then I guess some reading is in order.

 

[willis...]

Hey! i'm doing a project in spartan 3e using fpga! i'm really trying to do a clock but i can't do it ...i don't know even how too start.. =( somebody know how to do a clock using fpga ?? tks !

First, I would start by consulting these two pages...

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,792&Prod=S3EBOARD

**broken link removed**

The first link contains examples and reference material for the board that you are using.
The second link contains more code examples and reference material specific to the FPGA that is found on your board.
Both contain very useful information.

Now let us break down the possible meanings to your question.

1. Are you wondering how to access the system clock?
In order to access the system clock you will have to do a few things. First, you will need to consult your constraints file and find out to what pin the clock is attached from here, assuming you have already written some code, you can map the clock to a signal, which will then become the clock that you will use withing your code. If you want to use this clock withing your code as a conditional statement, you can use the rising/falling edge feature in vhdl...

if (falling_edge(clock)) then
               -- do something

2. You are trying to create a custom clock signal...
Once again, you will still need to access the system clock to perform any sort of counting or measurement. If you want to create a clock pulse, you can use the master clock to create a count and then alternate a signal based on the count.
Assuming a signal (std_logic_vector) "pulse" and an integer "count"

if (rising_edge(clock)) then
              count <= count + 1;
              if (count >= 0 and count < 10) then
                   pulse <= '0';
              elsif (count >= 10 and count <= 20) then
                   pulse <= '1';
              elseif (count > 20) then
                   count <= 0;

As you can see, the code snippet above takes the master clock and essentially divides it down. By keeping a count, you can create a pulsed "clock" signal.

If you need more help you will need to be slightly more specific regarding the nature of your problem. You will also most likely need to do some experimenting and research on your own.

Regards,
Willis

 

[hate]

Below is the code for a 3-digit BCD-Counter (Binary Coded Decimal) I implemented while studying Verilog. You have to change the compare values (I commented on the code) to make it count like a clock (i.e. up to 60 instead of 100) and you can also add more digits for a full scale clock. You can access the driver for the lcd here:
https://www.edaboard.com/threads/262755/
By the way you have to adjust the counter variable to increment by 1 after each second.

Regards...

module main(
	input wire clk,
	output wire lcd_rs,
	output wire lcd_rw,
	output wire lcd_e,
	output wire[3:0] lcd_data,
	output wire sf_ce0
);
//------------------------------------------------------------------------------
	localparam CMD=8'h00;
	localparam CHR=8'h80;
	localparam CODE_LENGTH=5'h14;

	reg lcd_trgr=1'b0;
	reg[7:0] lcd_code[CODE_LENGTH-1:0];
	wire[CODE_LENGTH*8-1:0] lcd_code_flat;
	wire lcd_busy;

	genvar pk_idx;
	generate
		for(pk_idx=0; pk_idx<CODE_LENGTH; pk_idx=pk_idx+1)
		begin: pack
			assign lcd_code_flat[8*pk_idx+7:8*pk_idx] = lcd_code[pk_idx][7:0];
		end
	endgenerate

	LcdMdl #(.L(CODE_LENGTH)) lcd (
		.clk(clk),
		.lcd_trgr(lcd_trgr),
		.lcd_code_flat(lcd_code_flat),
		.lcd_busy(lcd_busy),
		.lcd_rs(lcd_rs),
		.lcd_rw(lcd_rw),
		.lcd_e(lcd_e),
		.lcd_data(lcd_data),
		.sf_ce0(sf_ce0)
	);
//------------------------------------------------------------------------------
	reg[23:0] count=0;
	reg[3:0] bcd[2:0];


	initial begin
		bcd[0]=4'h0;
		bcd[1]=4'h0;
		bcd[2]=4'h0;
	end


	always @(posedge clk) begin
		if(lcd_busy)
			lcd_trgr<=1'b0;

		if(&count) begin
			bcd[0]= bcd[0]+ 1;

			if(bcd[0]==10) begin
				bcd[0]=4'h0;
				bcd[1]= bcd[1]+ 1;

				if(bcd[1]==10) begin    // Change '10' to '6' for 60 seconds.
					bcd[1]=4'h0;
					bcd[2]= bcd[2]+ 1;

					if(bcd[2]==10)
						bcd[2]= 4'h0;
				end
			end

			if(!lcd_busy) begin
				lcd_code[0]<= (CMD| 8'h01);
				lcd_code[1]<= (CHR| (bcd[2]+ 8'h30));
				lcd_code[2]<= (CHR| (bcd[1]+ 8'h30));
				lcd_code[3]<= (CHR| (bcd[0]+ 8'h30));
				lcd_code[4]<=8'h00;
				lcd_trgr<=1'b1;
			end
		end

		count<= count+ 1;
	end
endmodule

 

[AllanJ]

I suggest you should read some book about VHDL or Verilog HDL too.It may be much helpful for you.