spartan 3e starter UDP IP ethernet VHDL

[mckr]

Hi everyone,
I want to send data to PC from my FPGA. The board have SMC lan83c185 so I have used it as a psy layer. I have calculated the CRC and IP checksum values. Also ,I have sent true destination and source address. Moreover, I have tried in the simulation.And the results are true. When I tried the vhdl code on real board , there is any data in Wireshark. The Led of the ethernet card is blinking when the fpga sent data but no data in Wireshark.
How can I find the problem ? Thanks for all reply....

 

[Tetik]

Just one question for you. Do you use a crossover ethernet cable to connect the FPGA board to the PC? If not, use one or use an ethernet switch between.

 

[mckr]

No, I am using crossover cable .

 

[ads-ee]

You've supplied to little information for anyone to help (other than suggestions like checking for a crossover cable).

Is this a custom Ethernet MAC core you designed or IP that you bought/stole/found_under_trash_can?

What did you simulate? How did you simulate? Are you sure you exercised it correctly?

Without details of what you've done and how you did it. Any replies will just be guesses pulled from rear ends.

 

[mckr]

The code is owing to me. I want to write a very simple code to send data. I attached the code.

 

[FvM]

I quote your code below for other contributors convenience.

Presumed the signals are connected correctly and the PHY can work with it's default parameters and doesn't need initilization through managment interface (I believe, that's O.K.), are you sure that the packet you have placed in constant data is valid ethernet data? How did you verify it?

How is start triggered?

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mac is
    Port ( reset : in  STD_LOGIC;
           TX_CLK : in  STD_LOGIC;
           start : in  STD_LOGIC;
           TX_data : out  STD_LOGIC_VECTOR (3 downto 0);
           TX_en : out  STD_LOGIC
      );end mac;
architecture Behavioral of mac is
--the data for sening to computer 
constant data : STD_logic_vector (0 to 575 ):=X"55555555555555D500460937F72300463E011E2508004500002EB3FE000080110540C0A8002CC0A8000404000400001A2DE8000102030405060708090A0B0C0D0E0F1011B331881B";
signal counter_data : integer range 0 to  619:=0;
signal data_aux:std_logic_vector (3 downto 0) :=x"0";
signal enable: std_logic:='0';
type state_type is(
MAC_start,
data1,
endsend
);
signal current_state: state_type := MAC_start;
begin
process(TX_CLK,reset)
begin
   if(reset='1') then
     current_state<=MAC_start;
   elsif (TX_CLK'event and TX_CLK='0') then 
      TX_data<=data_aux;
      TX_en<=enable;
      case current_state is
         when MAC_start=>
            counter_data<=0;
            enable<='0';
            data_aux<=(others => '0');
            if(start='1') then
               current_state<=data1;
            else
               current_state<=MAC_start;
            end if;
         when data1=>
            enable<='1';
            data_aux<=data(counter_data to counter_data+3);
            counter_data<=counter_data+4;
            if(counter_data<572) then 
               current_state<=data1;
            else
               current_state<=endsend;
            end if;
         when endsend =>
            counter_data<=counter_data+1;
            enable<='0';
            data_aux<=(others=>'0');
            if(counter_data=618) then
               current_state<=MAC_start;
            else
               current_state<=endsend;
            end if;
      end case ;
   end if ;
end process;
end Behavioral;

---

 

[mckr]

Because I take that constant data from the https://www.fpga4fun.com/10BASE-T2.html. I have changed MAC address in the field. The start is triggered by simply pressing button on the board.

 

[FvM]

Is the address range 192.168.0.x belonging to your network segment and displayed in wireshark?

 

[mckr]

Yes ,that range is belongs to my network.
There is no receving packets in wireshark.

 

[Miralipoor]

Hi,
when you can not see any data, following circumstances may occur
1- you are not able to feed true preamp
2- delimiter byte is missing or is not in true position.
3- frame CRC corrupted or did not calculated correctly.
4- auto negotiation of phy is disabled.

I propose to test loopback first. loop back in phy layer and mac layer give you significant information.
Regards

 

[mrflibble]

Traditional problems are:
1 - no arp entries, and as such no data being sent.
2 - checksum wrong, and as such either a network device (switch, router) is not passing it along, OR an os network layer is not passing it along.

Regarding 2) usually a direct cable between board and test PC helps there.

Oh and I'm so lazy that these days I am assuming at least 1 side of the connection will have auto crossover. But since that's not always the case be double plus sure you test it with both a straight & a crossover cable, just in case you have made a real silly assumption somewhere.

You did inspect your packets on the fpga side with chipscope or some other means?

- - - Updated - - -

Since you say the led on the lan card in your pc in blinking (precisely when sending packets from the fpga) then at least the link layer stuff went okay.

And since you are sending from fpga to pc (using the correct MAC address obviously. right?) then most likely it is checksum. Assuming of course you are sure about the mac address, and the source & destination address. An assumption best not to make. Ever.

After that you should probably check firewall settings for that network interface.

 

[mckr]

Yes the connection is direct connection there is no switch etc.
The mac is correct. Actuaaly,wireshark captures the packets with wrong checksum ( I tried ) so I think that the problem is not related with checksums . Also, there is no firewall in my pc.
I tried following code in my board and it is worked very well. However, I did not understand the problem on my simple code.
http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/Spartan3E-500-UDP-Core/td-p/43578

 

[ads-ee]

See how adding your code to the post helps . Now you've got lots of suggestions.

One key take away I saw was that you changed the MAC address of the IP packet you sent. Are you absolutely sure you correctly computed the IP header checksum? Check out this link for how to compute the IP header checkum

I looked for the online IP header checksum calculator that I used once to verify a design I did in the past but can't seem to find it. It allowed you to put in a header and it would figure out what the checksum should be.

Anyway recheck your calculation following along with the link I posted. If you have the checksum wrong then the packet will be discarded (I'm assuming this would happen before wireshark even knows there is a packet)

Regards

 

[mrflibble]

Regarding checksum, yes you can capture packets with invalid checksum in wireshark. It will even get a nice bright color as a hint. Unfortunately the logic implication is a one way arrow. So I would keep the checksum on the list of possible suspects, just a lower priority suspect for when you have checked the others first.

However, if you use the wrong mac address you are boned. No matter how pretty the checksum is.

What you can do is:
- bring down interface
- bring up interface
- check the stats (ifconfig or ipconfig depending on linux vs windoze)

Pay attention to the error/dropped/overrun and RX/TX etc counts.

Then send some packets from fpga to pc and recheck counters. The change in counter values usually is a good hint.

 

[FvM]

It seems like only the MAC addresses are changed, they aren't part of the IP header and not included in any checksum.

The PHY should be sending the raw packets. But there may be all kind of hardware problems involved that we don't even think of.

How do you connect the PHY to the network, via switch or hub?
If it's a switch or hub, does it signal an existing link?
Does it signal packet receive?
If it's a switch, is the destination address equal to your PC running Wireshark?

 

[mckr]

The problem is not related with the checksums. I am almost sure about that. Also , I have checked the stats as @mrflibble suggest. However, I did not realized any meaningful result. Also the
connection does not include any switch or hub .there is a direct connection btwn PC and FPGA. As a shared before, I found some code in internet and it is worked very well.So the problem is on my code. I simulated the working code and its result and my code's result are same .

 

[mrflibble]

There is by definition a meaningful result. What stats did you get before? Then what traffic precisely did you send? And what stats did you get after sending? Copy/paste please.

- - - Updated - - -

Also, to be on the safe side: what kernel version? Because at least that way I get a "what kernel version, I use windoze xyz?".

 

[FvM]

I simulated the working code and its result and my code's result are same.

Means exactly what? The output to the PHY is byte-by-byte identical, also same idle time between packets? Rather unlikely, I presume.

On the other hand, the udpSender code is still simple. So why not reducing it stepwise to find out at which point the problem comes up?

 

[mckr]

I only simulated the inputs pf phy layer ( output of the mac sender).

Hımm, Reducing the working code is good idea, I will try