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Spartan 3E Starter Kit - DDR Problem

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alsig

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spartan 3e starter kit ddr

Hi,

I just bought a Spartan 3E Starter Kit from Xilinx and it seems that there is a problem with the DDR chip.

To make a simple test of the board I made a project in EDK including the DDR controller.
I also included the memory test and an uart for std i/o. When running the memory test all fails, (8, 16 and 32 bit) The project is made from the wizard and I've checked that the revision of the board is correct.

After a few hours of investigating it seems that I can write and immediately read it back, but if I "wait" a few lines of code the result is corrupted when I read it back.

I've check the ".ucf" file for any errors but it still doesn't work.

Is my board damaged?

Best Regard
Jens Ravn Alsig
 

banjo

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spartan 3e starter kit memory test fails

Are you writing to a single memory location in the DDR DRAM or multiple locations. If you are writing to a single location, then it is possible that the data is still on the bus which you immediately read back. If you are writing to multiple locations and all locations are correct when you read back immediately, but fail after some time, then it sounds like the controller in the FPGA is not running the DRAM refresh cycles.

DDR DRAMs require proper setup through the mode register commands before they will operate. They are not just power up and go devices. The controller code within the FPGA needs to be compiled with the proper DRAM settings for the devices included in your board. Without these settings, the DRAM will not be properly initialized and will never work. Make sure that these parameters are being passed into the controller. Look at your Synthesis warnings to make sure that it is not just taking some arbitrary default values.

Did the Starter Kit come with any demo bit files? If it has a memory demo bit file, you could load this to at least test the board.
 

alsig

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spartan 3e starter kit memory test failes

The memory test that I ran was the one that was auto generated by the EDK software and it writes multiple addresses. If I remember correctly it writes 1024 addresses in the 32 bit test, 2048 in the 16 bit test and 4096 in the 8 bit test.

I think that the DDR chip and controller is properly configured because I used the wizard from Xilinx to generate the bitstream.

The board was programmed when I received it but the DDR chip wasn't used in this program.

Is there anybody that can generate a bitstream that accesses the DDR chip and writes the result to the UART?
 

channing

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spartan3e opb_ddr

Were you using the EDK 9.1i for your design? And were you using the opb_ddr 2.00.c? If so, you can change the opb_ddr to 2.00.b and try again.

Hope it helps.
 

amemsyco

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edk spartan 3e code

Hello, just want to tell everybody that the solution suggested by channing works for me. Change the version of mch_opb_ddr to 1.00.b (I simply edited the *.mhs file and changed the 'c' to 'b'). I'm using EDK 9.1.02i and I had the same problem with my board. Thank you channing!
 

ship_baba

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spartan3e ddr

just take a reference desing to try out or make support log in xilinx
 

amemsyco

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sparton 3e starter kit ddr

Hi! Just found this answer in the Xilinx Answer Database.

**broken link removed**

However, I haven't tried it yet.

EDIT: I have tried the solution now and it works.
 

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