spartan 3e running problem

[tigertag]

Hi

I am using Xilinx Ise 10.1 with Spartan-3e FPGAs. I have a strange problem. My program is reading data from a pin and then runs a finite state machine structure to determine the response. I made a test port, directed some signals to the test ports and connected a logic analyser to the test ports to debug the program. The program was running well. However when i deleted the test port the program is not running correct. When i add test pins to see the signals the program starts running correct again. By the way the test pins are not connected to anywhere else and are not used in any part of decision making algorithm. Could you please help me with the problem.



Hakkı KAPLAN

Udea Electronics

 

[user_asic]

How many slices is your design using?

I've seen this with my designs where after adding debugging capabilities, the design works very well. But when this feature is removed, the design completely breaks. After you remove the debug capability, you may violate some of the timing constraints or paths. I've found it best to just leave the debug capability in the final design.