Spartan 3E Digital Clock Manager Problem

[newbie123FPGA]

I am using a DCM to go from 50 MHz to 25 MHz.This code was just for confirmation and it doesn't work.I've listed 'clk' as output to view DCM output.It's exactly hal of input CLK, as it should be.When I change to @posedge CLK, the simulation works, with the DCM output clock, the always block doesn't seem to be working.

Simulation : https://obrazki.elektroda.pl/4112796400_1478817837.jpg

module v(
    input CLK,
    input RESET,
    output reg counter,
    output clk
    );
    clo instance_name (
    .CLKIN_IN(CLK), 
    .CLKFX_OUT(clk), 
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT)
    );

	
	always @ (posedge clk)
	begin
	if(RESET)
	counter <= 0;
	else
	counter <= ~counter;
	end

 

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Your reset isn't active when clk is active so counter is never reset to 0.

Don't use names that are only different by the case of the name! This is a big no-no and just makes your code confusing. Also if you develop this bad habit, if you ever start using VHDL all your signals that you named with different cases will be shorted together.