SPARTAN-3 F-LUT AND G-LUT

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spartan 3 luts:

Hi all,

For Spartan-3 We have CLB and inside each CLB there is LUTs. I know all component inside each CLB but in each CLB there is 8 4-Bit Input LUTs.

These LUTs called G-LUT and F-LUT. I want to know what is inside each LUT?

because when I have different design like A.B or (( A.B.C.D) + (A+B+C+D)) still same number of gates use for both design!

So I like to know what is exactly inside each LUT? I could not find any informtion in Spartan-3 datasheets about inside these LUTs.

Are these LUTs (Look-Up Table) are simply a block of memory containing a complete table of all possible input combinations or something else?

If anyone knows about archtucture of these LUTs please let me know.

Thank you

Pouya!
 

what is inside a lut

There is no mistery in the slice.
Pick the DS099.pdf document ( Spartan-3 FPGA Family: Complete data Sheet ) from the Xilinx site and look at the page No. 11.

Apparently, you haven't red all important files

Regards, yego
 

inside a lut

An equation translate to a truth table. That is, the LUT is simply a look-up table which take the inputs, and according to it, look up in a table and output either a 0 or 1. a 4-input LUT is simply a 16x1 ROM-like structure.

So, wether you use a simple equation like A.B or a more complex therm (which use up to 4 input), both will use a complete LUT.

Gates evaluation is very approximative. The software only count the number of LUT, FF, ... used and convert this to a number of gates. It doesn't look at original equations.
 

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