Source sharing in matched devices

[ripoo82]

I am looking for a good methodology for sharing of source terminals in matched devices.

Has the sharing of sources any impact in a current mirror? Is there any mismatch introduced by STI stress or LOD effects?

Would you say it is a good idea to never share the source between matched devices in an STI process?

 

[rangermad]

For the best matching step your transistors with no S/D sharing. If area becomes a problem then you need to start making some tradeoffs. I prefer to use an even number of fingers for transistors in a current mirror. You can share the drains but not sources and get good matching with a little tighter layout than stepping the transistors.

 

[ripoo82]

Is it correct to assume that STI stress is an non-linear effect?
If so, overlapping sources in a matched array will cause a mismatch. Even if the layout is perfect common centroid.

Is it correct to assume that problems with STI stress start to arise from nodes below 130nm?

 

[rangermad]

In a "perfect common centroid" all gates will see the same geometries in the source direction and the same geometries in the drain direction. So the STI stress would be the same for each transistor.

 

[ripoo82]

Only if you don't overlap the sources. If you place 2x2 transitors with 2 fingers in an XYYX configuration (perfect common centroid), the source can be overlapped if connectivity is the same. LOD effects Sa and Sb will not be the same for transistor X or Y. Y is more to the center, so less affected by STI stress.

If you don't overlap the source, I assume STI effects are equal.