Source code encryption in Verilog-XL or NC-verilog

[kunjalan]

Hi,
Please use Verilog-XL or NC-verilog. You can encrypt your source code.
Please use 'protect and 'unprotect option to your source code.
You can encrypt your source code from start line to end line that you want to protect.
But once you have protected your source code, you can not decrypt your code. You can olny simulated it. So, original code should be saved another saving directory.

 

[allegro]

ncverilog protect

So it doesn't make sense.

 

[kittykat77]

`protect verilog

Yes, it does make sense. Supposedly that you are an IP vendor and you claim that you have a verilog code which does a specific function. Rather than send to the potential customer a readable RTL code - the vendor simply encrypts it and let the customer verify through simulation .
If the customer is happy with the simulation results - then maybe he/she will then want to buy the synthsizable code.

The encryption is simulator dependent - which means that if it is encrypted using verilog-xl, then the recipient of that encrypted code must also have verilog-xl to simulate it with.

Altera megacore is another method which allow Altera to allow its potential customers verify the validity of its IP cores using yet another encryption procedure.

 

[bigrice]

verilog `protect


can anyone decrypt the protected code?

 

[niko_zhang]

verilog protected

how modelsim simulate with this files