Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Some wrong with this verilog-A file!!

Status
Not open for further replies.

wjxcom

Full Member level 5
Joined
Sep 7, 2005
Messages
281
Helped
4
Reputation
8
Reaction score
3
Trophy points
1,298
Activity points
3,840
Dear all:
I have a problem for simulating a simple file by HIPICE.
When I click the simulate, the result always tell me

** error **
During Verilog-A Device processing:
CML file does not exist
'C:\Documents and Settings\wjx197733\hsp-model-cache\1.34\D\\EXERCISE\DesignOPA\\lib.win32\ACOPEN.cml'

but in the license file, I can find the hspiceva feature
Why? what mistake is made by me?
Could you help me ?

Thanx a alot, help me please!!!

The va file is:

// when analysis is ac , Open the circuit with DC oppoint

`include "constants.vams"
`include "disciplines.vams"

module acOpen(Vout,Vin);
output Vout;
input Vin;
voltage Vout,Vin;

analog
begin
if(!analysis("ac","noise"))
V(Vout) <+ V(Vin);
end
endmodule

Added after 2 hours 30 minutes:

Hi all: I set up Hspice 2006.9 again and the error vanished!

thanx!!!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top