Some questions on digital logic and microprocessors

[kumar_eee]

Written Test

1. If a layer 4 transfers data at the rate of 3000 bytes/sec. What will be the size of data block transferred by Layer 2

2. Consider an alternate binary number representation scheme, wherein the number of ones M, in a word of N bits, is always the same. This scheme is called the M-out-of-N coding scheme. If M=N/2, and N=8, what is the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint, consider that the number of unique words represent able in the latter representation with N bits is 2^N. Hence the efficiency is 100%)

a. Close to 30%
b. Close to 50%
c. Close to 70%
d. Close to 100%


3. A CPU supports 250 instructions. Each instruction op-code has these fields:

-----The instruction type (one among 250)
-----A conditional register specification
-----3 register operands
-----Addressing mode specification for both source operands

The CPU has 16 registers and supports 5 addressing modes. What is the instruction op-code length in bits?

a. 32
b. 24
c. 30
d. 36

4. State which of the following gate combinations does not form a universal logic set:

a. 2-input AND + 2-input OR
b. 2-to-1 multiplexer
c. 2-input XOR + inverter
d. 3-input NAND


5. In a given CPU-memory sub-system, all accesses to the memory take two cycles. Accesses to memories in two consecutive cycles can therefore result in incorrect data transfer. Which of the following access mechanisms guarantees correct data transfer?

a. A read operation followed by a write operation in the next cycle.
b. A write operation followed by a read operation in the next cycle.
c. A NOP between every successive reads & writes
d. None of the above

 

[jraks]

Written Test

first question

now these layers are inrespect to the OSI model or the TCP/IP model or any other clarify
and if OSI then layer 2 is the datalink layer and layer 4 is the transport layer
in the TSP/IP Model layer 2 is the datalink layer and layer 4 is the application layer
and both the models do not depend on the transfer speed as it is common through all the layers and hence the block size is 32bit

Added after 13 minutes:

question 4

we cannot get a universal logic set using a three input NAND with others we can get

Added after 3 minutes:

question 5

if you have seen the actula timing daigram of any microprocessor then the actual answer would be none of the above

 

[eecs4ever]

Re: Written Test

jraks:
Question 4. you can build a 2 input NAND out of a 3 input NAND by tieing 1 input to 1. and 2 input NAND forms a universal logic set.


the answer should be C. you cannot use xor and not to build AND .

 

[jraks]

Written Test

if you would have seen the question more clearly
with a single NANDgate we cannot get all the logics
therefore a single three input cannot form the universal logic set

 

[eecs4ever]

Written Test

jrak,

can you get all the logics using xor + inverter?
please show me how to make AND.

Thanks