Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

some questions about pll ADF4252BCP.

Status
Not open for further replies.

dushan1

Member level 2
Joined
Jun 24, 2004
Messages
45
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
309
the vco out frequency is 320~380MHz ,step frquency 1.25KHz.the reference oscillator is 10MHz,R=5,so the PFD =2MHz,all the frequency can lock well ,but when the pll is locking,there is a 344MHz frequency out,the power is -90dbm.when i change the register N,the 334MHz not change ,when i power down the vco,the 334MHz still stands here. my reference oscillator is sine wave ,no harmonics.when i change the PFD=5MHz,the frequency changes.I want to know whether the ADF4252
will oscillator in such frequecy range .how to avoid it?
thanks!
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top