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Some problems with video filterin on FPGA

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MSUstudent

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Hello,
We would like to write a code for video processing on Development board with FPGA (Xilinx and Altera). On this board no Signal Processor, but I read documentation and undestood, that processor can be realised on FPGA by using processor core. Do you know, how does many percent of all Logic Elements this "software processor" use, and how shall we write code for this processor? Do you know any programs, that can convert code on C to special code for FPGA (for example Verilog, Vhdl etc.)? And do this programs have a Debug code features (for example, we would like to know values on each FPGA out in smth. time momemt)?
Can you advise any emulators of FPGA, which can be run on PC?
Next problem: we must to filtering video. We have a video file on PC, and would like to have a Video file after processing. What interface, which can be on Development board, is more better to this? We think that is a PCI/PCI-Ex or Ethernet, but you may be have another opinion.
 

1. Look at NIOS from Altera, MicroBlaze from Xilinx for size/performance characteristics. Also keep in mind soft processor is not enough to do video filtering applications.

2.C to VHDL/verilog use google search

3. to debug FPGA you can use chipscope from xilinx, or logic probe from Altera


3. You can use USB or Ethernet to get your data from PC to the development board
 

This doesn't directly answer your questions, but . . .

A general-purpose CPU implemented in FPGA logic (such as NIOS and MicroBlaze) has very poor performance compared to a dedicated silicon CPU (such as a Pentium). Even a modern Pentium is stressed trying to do video processing.

For high performance, consider building video parallel processing stages with native FPGA resources such as multipliers, block RAMs, accumulators, etc. You could build these stages yourself, or you may find IP cores for 2D filters, convolution, compression, etc. Or maybe try a MATLAB based tool such as Xilinx System Generator for DSP.
**broken link removed**

Maybe some of these Xilinx application notes will help you:
**broken link removed**
 

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