Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Some problems about Spice netlist transfered from Verilog netilst after synthesis.

Status
Not open for further replies.

elliot_cai

Newbie level 4
Newbie level 4
Joined
Apr 5, 2008
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,323
Hello!
I get a Verilog netlist after synthesis and convert it Spice netlist by nettran, I want use this Spice netlist inputting Nanosim for simulation.
But some problems in the Spice netlist:
1. The Verilog netlist hasn't power and ground connections, so in the Spice netlist also missing the connections. What can I do add the connections during the synthesis?
2. In the Verilog netlist, the pin orders are not so crucial. But in Spice netlist, when it calls the sub cells, the pins orders should be uniform. Since my Spice netlist it converted from the Verilog netlist, the pin orders is the same with the Verilog netlist but different from the Spice sub cells I defined before. What can I do adjust the pin orders? Can it be mapped in the synthesis?
Thanks!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top