some problems about pipelined ADC

[lhlbluesky]

for pipelined ADC, if i use 0.18um technology, and sampling rate is 15Ms/s, resolution is 10-bit, per stage 1.5-bit, then what is the proper value of static power consumption? are there some related papers which give the simulation or testing results?

besides, when fin=7.5M, ENOB=7.7, SFDR=51dB, INL=+-6LSB, are these parameters normal? i saw some papers, when in mid-frequency, the ENOB\INL\DNL\SFDR etc, still very well. then what is the possible reason for my ADC, which factors can cause the bad results?

pls help me, i'm terribly confused, can anyone give me some advice or some reference papers? thanks all for reply.

 

[lhlbluesky]

can anyone help me, pls?

 

[yxo]

I don´t know about power, but your ENOB, SFDR, INL are _very_ bad. How did you measure them? There are a a huge amount of errors, such as low gain of the amplifiers, CMFB doesn´work, some transistors aren´t in saturation and so on. Draw you attention to S/H first.

Added after 39 seconds:

Your ENOB must be about 9.5

 

[lhlbluesky]

my ADC is used in CMOS Image Sensor,before ADC,a DPGA is used which can realize S/H function.
so, there is no S/H in my ADC.

then, what is the possible reason? can anyone explain to me clearly about the seperate affecting factors?

 

[lhlbluesky]

any ideals?