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Some problem in setting DDR layout constraints in Allegro?

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gr1x

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I'm laying out a board with a ddr slot. As there is many constraints I have to set in Allegro 15.0, expecially about "total etch length" and "relative propagation delay".
I found these steps in tedious when set constraints.

-------- U1.E5 R1.1 ----------------- R1.2 J3.3 ------------- J3.3 R2.1------------
| MCU | -----------> | serial resistor | ------------> | SO-DIMM | -------> | parallel R
-------- Net D0 ------------------ Net DA0 ------------- Net DA0 -----------

when I set "total etch length", as component J3's Pin 3 is just a pad, allegro treat the trace from resistor R1.2 to resistor R2.1 as the some net, so I've manually edit net net DA0's property, write "R1.2:J3.3:500:600", to set the length between R1.2 to J3.3(SODIMM slot J3 pin 3) with 500mils to 600mils. After I've laied out the trace between R1.2 to J3.3, then I've to edit net DA0's property again, write "J3.3:R2.1:400:500". It's troublesome and time wasting to do all these work. But if I didn't set these constraints, I won't know whether the trace I layout is within the length constraint.

I know allegro can show the dynamic length when laied the trace first, but when I adjust the trace(ex."snake" this trace) , Allegro didn't show any info about trace length. So I've to set the abovue rules manually.

It's there anyway to simplify these steps in Allegro? I'm not using sepcctra, isn't there any way to equalize net is Allegro?
 

majnoon

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Re: Some problem in setting DDR layout constraints in Allegr

Yes it is.
You should use RPD in this case and use Xnets property then you can assign a net as your target eg CLK and route manually DDR nets with respect to this target with a value for RPD.

Regards,
M
 

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