some problem about input delay and output delay

[jinruan]

hi guys,
who can tell me how to deal with the following case?

i have two clock clk1 and clk2 in my design,
clk1 is a input signal and clk2 is a gated clock, input1 and input2 are relative to
clk1 and input3 and input4 are relative to clk2, how can i define the input delay?
i define as belows but failed:
set_input_delay 5.0 -clock clk1 {input1 input2}
set_input_delay 20.0 -clock find(pin "SYNU0/U1/clk2") {input3 input4}

what's the problem?

 

[honeyxyb]

you should define clk2 as a clock.

 

[jinruan]

i have define clk2 as a clock(but it is a internal pin),
but it failed. the question is if the clock is a gated clock(it's a internal pin, in other words, it's not output to the top module), how can i define input|output delay to this clock?

 

[spauls]

are u getting compilation error or logical error ?

 

[jinruan]

it indicate that can't find the clock "clk2"

 

[eda_wiz]

hi guys,
who can tell me how to deal with the following case?

i have two clock clk1 and clk2 in my design,
clk1 is a input signal and clk2 is a gated clock, input1 and input2 are relative to
clk1 and input3 and input4 are relative to clk2, how can i define the input delay?
i define as belows but failed:
set_input_delay 5.0 -clock clk1 {input1 input2}
set_input_delay 20.0 -clock find(pin "SYNU0/U1/clk2") {input3 input4}

what's the problem?

I guess this is not possible unless the gated clock is being generated is a periodic signal. bcoz the gated output is just an asynchronous pulse if ENable occurs at some random time durations..

if you know the relation between gated clock and the actual clock(incase it is fixed) you can define a virtual clock for the same period, and use that virtual clock for calculating input_delay..

hope it helps

rgds