jinruan
Junior Member level 3
hi guys,
who can tell me how to deal with the following case?
i have two clock clk1 and clk2 in my design,
clk1 is a input signal and clk2 is a gated clock, input1 and input2 are relative to
clk1 and input3 and input4 are relative to clk2, how can i define the input delay?
i define as belows but failed:
set_input_delay 5.0 -clock clk1 {input1 input2}
set_input_delay 20.0 -clock find(pin "SYNU0/U1/clk2") {input3 input4}
what's the problem?
who can tell me how to deal with the following case?
i have two clock clk1 and clk2 in my design,
clk1 is a input signal and clk2 is a gated clock, input1 and input2 are relative to
clk1 and input3 and input4 are relative to clk2, how can i define the input delay?
i define as belows but failed:
set_input_delay 5.0 -clock clk1 {input1 input2}
set_input_delay 20.0 -clock find(pin "SYNU0/U1/clk2") {input3 input4}
what's the problem?